PCI Bus Transactions

When any of these conditions is not met, the 21555 uses the memory write command. When a subsequent cache line in the transaction does not have all bytes enabled, the 21555 terminates the MWI transaction and delivers the remaining data using a memory write command.

The 21555 continues the MWI transaction as long as a full cache line is posted in the posted write queue. A a full cache line corresponds to the cache line size of the target bus. When the 21555 is within one data phase of delivering a complete cache line and there is not another full cache line posted in the queues, the 21555 master terminates the transaction at the cache line boundary. For example: 1 Dword for 32-bit transactions or 2 Dwords for

64-bit transactions. This can occur because:

•The transaction has terminated on the initiator bus at a non-cache line boundary.

•The write data is being pulled from the queue faster than it is being posted. In this, a full cache line is not posted soon enough to continue the MWI.

When the 21555 terminates an MWI transaction before all write data is delivered, it initiates another write transaction to finish delivery of the write data. When a fraction of a cache line remains, the 21555 initiates the transaction with the memory write command. When at least a complete cache line was subsequently posted, then the 21555 once again initiates the transaction with an MWI command.

5.2.364-bit Extension Posted Write Transaction

The 21555 uses the 64-bit extension signals, when implemented, for accepting and delivering posted write data.

As a target, the 21555 asserts ACK64# in response to the initiator’s assertion of REQ64# for memory writes and MWI commands if the address is Quadword aligned (address bit AD[2] is zero). The 21555 then accepts 64 bits of data per data phase without inserting target wait states.

As an initiator, the 21555 asserts REQ64# when delivering posted write data as long as the burst consists of a minimum of 4 Dwords, and the original address is Quadword (64-bit) aligned. When the target asserts ACK64#, write data is delivered 64 bits per data phase without inserting master wait states. When the burst ends on an odd Dword address boundary, the 21555 forces the high four byte enables of the last data phase in the burst to be deasserted.

5.2.4Write Performance Tuning Options

The 21555 implements several features and options that affect write performance when forwarding posted write transactions

5.2.4.1Memory Write and Invalidate

When the MWI Enable bit in configuration space is set for that corresponding interface, the 21555 is enabled to initiate MWI transactions as described in Section 5.2.2.

5.2.4.2Fast Back-to-Back

The 21555 may be enabled to initiate fast back-to-back transactions. The 21555 must have the bus grant the clock cycle before it asserts FRAME# for the second transaction, and the Fast Back-to-Back Enable bit must be set for the interface on which the 21555 is initiating the transaction. When both of these conditions exist, the 21555 may initiate the second transaction with fast back-to-back timing following a write transaction that is not terminated with STOP#.

52

21555 Non-Transparent PCI-to-PCI Bridge User Manual

Page 51 Page 53
Page 52
Image 52
Intel 21555 user manual 3 64-bit Extension Posted Write Transaction, Write Performance Tuning Options
Page 51 Page 53

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
Top Page Image Contents