Microarchitecture | Intel 21555 guide

Introduction

Figure 2 shows the 21555 microarchitecture.

Figure 2. 21555 Microarchitecture

215555
	Downstream Delayed Buffer
	Downstream Posted Write Buffer
	Upstream Read Data Buffer
	Downstream Read Data Buffer
	Upstream Posted Write Buffer
rimary	Upstream Delayed Buffer					Secondary
	Upstream Delayed Buffer					PCI
						PCI
PCI						Bus
Bus
Primary						Secondary
Target		Device-				Target
Control	Primary	Device-		CSR	Secondary	Control
	Config	Specific		CSR	Config
	Config	Config	Registers		Config
	Registers	Config	Registers		Registers
	Registers	Registers			Registers
Primary		Registers				Secondary
Primary						Secondary
Master						Master
Control						Control
JTAG		ROM				Secondary
JTAG		Interface				Bus
		Control				Arbiter
JTAG Signals		ROM Interface		Interrupt		Secondary Arbiter
		Signals		Signals		Signals
						A7418-01

21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Intel 21555 user manual Microarchitecture

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.

Contents

Non-Transparent PCI-to- PCI Bridge Page Contents With SROM, Local, and Host Processors 10.1 Tables Figures 131 148 108 Page Preface Brief description of the contents of this manual follows Numbering Data UnitsTerm Words Bytes Bits STS Signal NomenclatureSignal Type Abbreviations Signal Description Type Register Abbreviations Access Type DescriptionRegister Abbreviations Comparing a 21555 to a Transparent PPB Introduction CPU Dram PCI ROMCPU PCI Feature PPB Feature Comparison Control Logic Architectural OverviewData Buffers Registers Microarchitecture Secondary Bus VGA Support Special ApplicationsProgramming Notes Primary Bus VGA Support Transaction Forwarding ROM AccessPage Signal Pin Functional Groups Signal DescriptionsGroup by Signal Pin Description See Primary PCI Bus Interface Signals Sheet 1 Primary PCI Bus Interface SignalsSignal Name Type Description Pstopl Primary PCI Bus Interface Signals Sheet 2Ppar Preql Pad6332 Primary PCI Bus Interface 64-Bit Extension SignalsPrimary PCI Bus Interface 64-Bit Extension Signals Sheet 1 Pack64l Pad6332 , pcbel74 , and ppar64 to valid logic levels Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2Ppar64 Preq64l Secondary PCI Bus Interface Signals Sheet 1 Secondary PCI Bus Interface Signals Strdyl Secondary PCI Bus Interface Signals Sheet 2Spar Sstopl Scbel74 Secondary PCI Bus Interface 64-Bit Extension SignalsSack64l Sad6332 Miscellaneous Signals Miscellaneous SignalsPage Address Decoding Expansion ROM Address Mapping Decoding CSR Address DecodingMemory 0 Transaction Address Decoding BAR Setup Register Example Using the BAR Setup Registers Address Format Direct Address Translation Direct Offset Address Translation Lookup Table Based Address Translation Upstream Memory 2 Window Size Address Translation Using a Lookup Table Upstream Lookup Table Address Translation Lookup Table Entry Format Lookup Table Entry Format Forwarding of 64-Bit Address Memory Transactions Indirect I/O Transaction Generation I/O Transaction Address Decoding Address Decoding Type 0 Accesses to 21555 Configuration Space Configuration AccessesSubtractive Decoding of I/O Transactions Initiation of Configuration Transactions by Address Decoding Bar Summary 21555 Bar SummaryBar Size Address Translation Page Transactions Overview PCI Bus Transactions Posted Write Transactions Memory Write and Invalidate Transactions Memory Write Transactions 3 64-bit Extension Posted Write Transaction Write Performance Tuning Options Write-Through Delayed Write Transactions Delayed Write Transaction Target Termination Returns Delayed Read TransactionsTarget Bus Response Initiator Bus Response Nonprefetchable Reads Delayed Read Transaction Target Termination Returns Read Performance Features and Tuning Options Prefetchable Read Transactions Using the 64-bit ExtensionPrefetchable Reads Prefetch Boundaries Prefetching 64-Bit and 32-Bit Transactions Initiated by Read Queue Full Threshold Tuning Target Terminations Returned by Target Terminations Ordering Rules Transaction Termination Errors on the Target Bus Transaction Ordering Rules PCI Bus Transactions Page Power Management, Hot-Swap, and Reset Signals Sheet 1 Power Management, Hot-Swap, and Reset SignalsInitialization Requirements Srstinl Reset BehaviorPower Management, Hot-Swap, and Reset Signals Sheet 2 Spmel Prstl Reset Mechanisms 21555 Initialization Central Function During Reset Without Serial Preload With SROM, Local, and Host Processors Without Host Processor Power Management SupportWithout Local Processor Without Local Processor and Serial Preload 2 PME# Support Transitions Between Power Management StatesPower Management Actions Next Power State Action CompactPCI Hot-Swap Functionality Power Management Data RegisterOverview of CompactPCI Controller Hardware Interface Prstl 332 Ω Insertion and Removal ProcessPrimary Lstat K Ω Initialization Requirements 4b Insertion W DisconnectedW Connected 2a INS ENUM# Initialization Requirements Clocking Primary and Secondary PCI Bus Clock SignalsPrimary and Secondary PCI Bus Clock Signals Sheet 1 Signal Name Description Sclko Primary and Secondary PCI Bus Clock Signals Sheet 221555 Secondary Clock Outputs Sclk 66 MHz Support Page Parallel ROM Interface Interface Signals Signal Type Description Name Prom Interface Signals Sheet 1 Prom Interface Signals Sheet 2 WE# OE# Prom Read by CSR AccessParallel and Serial ROM Connection 21555 Prom Read Timing Prom Write by CSR Access Prom Write Timing Prom Dword Read Read and Write Strobe Timing Access Time and Strobe Control Attaching Additional Devices to the ROM Interface Attaching Multiple Devices on the ROM Interface Sromsrom Preload Operation Srom Interface SignalsSrom Interface Signals Serial ROM Interface Srom Operation by CSR Access Srom Configuration Data Preload Format Serial ROM Interface Srom Write All Timing Diagram Srom Erase Timing Diagram Page Secondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration SignalsSecondary PCI Bus Arbitration Signals Primary PCI Bus Arbitration Signals Primary PCI Bus Arbitration Secondary Bus Arbitration Using the Internal ArbiterSecondary PCI Bus Arbitration Secondary Arbiter Example Arbiter Control Register Secondary Bus Arbitration Using an External ArbiterBit Name Description Interrupt Support Primary and Secondary PCI Bus Interrupt SignalsPrimary and Secondary PCI Bus Interrupt Signals Interrupt and Scratchpad Registers Interrupt and Scratchpad Registers Scratchpad Registers Doorbell InterruptsPage Primary PCI Bus Error Signals Error HandlingError Signals Primary PCI Bus Error Signals Secondary PCI Bus Error Signals Parity Error Responses Sheet 1 Parity ErrorsType PER † Action Taken Error Transaction Error Transaction Parity Error Responses Sheet 2Asserts pperrl Asserts sperrl Parity Error Responses Sheet 3 System Error SERR# Reporting Jtag Signals Jtag SignalsJtag Test Port Initialization Test Access Port Controller Inbound Message Passing I2O Support I2O Support Outbound Message Passing 116 117 Page Reading VPD Information VPD Support Writing VPD Information Theory of Operation Chapter Register Reference Information List of RegistersRegister Summary Register Cross Reference Table Register Name Preload Hex Access Configuration RegistersConfiguration Space Address Register Sheet 1 Byte Reset Value Write Read Configuration Space Address Register Sheet 2 Configuration Space Address Register Sheet 3 Configuration Space Address Register Sheet 4 CSR Address Map Sheet 1 Configuration Space Address Register Sheet 5Register Name Reset Value Write Access Read Access Control and Status Registers CSR Address Map Sheet 2 Ffff W1TS CSR Address Map Sheet 3Ffff W1TC CSR Address Map Sheet 4 Primary CSR and Downstream Memory 0 Bara Sheet 1 Address DecodingPrimary and Secondary Address CSR Address Map Sheet 5 Secondary CSR Memory BARsa Sheet 1 Primary CSR and Downstream Memory 0 Bara Sheet 2 Primary and Secondary CSR I/O Barsa Secondary CSR Memory BARsa Sheet 2Offsets Primary CSR I/O BAR Secondary CSR I/O BAR Offsets Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BARUpstream I/O or Memory 0 BAR Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR Upstream Memory 2 Bar Upper 32 Bits Downstream Memory 3 Bar Translated Base Offsets Downstream I/O or MemoryXlatbase Downstream Upstream Offsets Memory Translated Base Upstream I/O or Memory Setup 139 Upper 32 Bits Downstream Memory 3 Setup Register Configuration Transaction Generation Registers Cfgaddr Downstream and Upstream Configuration Address Registers Cfgdata Configuration Own Bits Register Configuration CSR Sheet 1 Ioaddr IA Configuration CSR Sheet 2Downstream I/O Address and Upstream I/O Address Registers Offset Downstream I/O Address Upstream I/O Address Iodata Downstream I/O Data and Upstream I/O Data RegistersO Own Bits Registers Offsets Downstream I/O Data Upstream I/O Data Lookup Table Offset Register O CSRLutoffset Upstream Memory 2 Lookup Table Configuration RegistersPCI Registers Lookup Table Data Register Device ID Register Primary Interface Configuration Space Address MapSecondary Interface Configuration Space Address Map Vendor ID Register Primary and Secondary Command Registers Sheet 1 Primary and Secondary Command RegistersOffsets Primary Command Secondary Command Offsets Primary Status Secondary Status Primary and Secondary Command Registers Sheet 2Primary and Secondary Status Registers Sheet 1 SERR# Revision ID Rev ID Register Primary and Secondary Status Registers Sheet 2 Offsets Primary Cache Line Size Secondary Cache Line Size Primary and Secondary Class Code RegistersPrimary and Secondary Cache Line Size Registers Offsets Primary Class Code Secondary Class Code BiST Register Header Type RegisterOffsets Primary MLT Secondary MLT Primary and Secondary Interrupt Line Registers Subsystem Vendor ID RegisterSubsystem ID Register Enhanced Capabilities Pointer Register Primary and Secondary Minimum Grant Registers Primary and Secondary Interrupt Pin RegistersPrimary and Secondary Maximum Latency Registers Device-Specific Control and Status Address Map Device-Specific Control and Status RegistersChip Control 0 Register Sheet 1 Chip Control 0 Register Sheet 2 Chip Control 0 Register Sheet 3 Chip Control 0 Register Sheet 4 Chip Control 1 Register Sheet 1 Chip Control 1 Register Sheet 2 Chip Status Register Chip Control 1 Register Sheet 3I20ENA 163 Rots Generic Own Bits Register I2O Inbound PostList Status 16.6 I2O RegistersI2O Outbound PostList Status I2O Outbound PostList Interrupt Mask I2OOUT P I2O Inbound PostList Interrupt MaskI2O Inbound Queue I2O Outbound Queue I2O Outbound PostList Head Pointer I2O Inbound FreeList Head PointerI2O Inbound PostList Tail Pointer I2O Outbound FreeList Tail Pointer Ldifc W1TLS I2O Inbound PostList CounterI2O Inbound FreeList Counter Ldipc W1TLS I2O Outbound FreeList Counter I2O Outbound PostList CounterLdopc W1TLS PMD0 W1TC Interrupt RegistersChip Status CSR Chip Set IRQ Mask Register Upstream Page Boundary IRQ 0 Register Chip Clear IRQ Mask RegisterPAGE0IRQ W1TC Upstream Page Boundary IRQ Mask 0 Register Upstream Page Boundary IRQ 1 RegisterUpstream Page Boundary IRQ Mask 1 Register Primary Set IRQ Primary Clear IRQ and Secondary Clear IRQ RegistersPrimary Set IRQ and Secondary Set IRQ Registers Primary Clear IRQ Secondary Clear IRQ Secondary Set IRQ Mask Primary Set IRQ Mask and Secondary Set IRQ Mask RegistersScratchpad 0 Through Scratchpad 7 Registers Sheet 1 Primary Clear IRQ Mask Secondary Clear IRQ Mask Scratchpad 0 Through Scratchpad 7 Registers Sheet 2 Prom RegistersPrimary Expansion ROM BAR Sequence on Primary Expansion ROM Setup Register ROM Data Register ROM Setup RegisterRomdata ROM Control Register Sheet 1 ROM Address RegisterRomaddr Srompoll Mode Setting Configuration Register Sheet 1Srom Registers ROM Control Register Sheet 2 Serial Preload Sequence Sheet 1 Mode Setting Configuration Register Sheet 2Byte Description Offset Serial Preload Sequence Sheet 2 Serial Preload Sequence Sheet 3 Arbiter Control Error Registers Secondary SERR# Disable Register Primary SERR# Disable Register Init Registers Power Management ECP ID and Next Pointer RegisterPM ECP ID PME Power Management Capabilities RegisterAPS DSI Pmcsr Bridge Support Extensions Power Management Control and Status Register Reset Control Register Power Management Data Register HS Next Pointer CompactPCI Hot-Swap Control Register Sheet 1 CompactPCI Hot-Swap Control Register Sheet 2 Jtag RegistersJtag Instruction Register Options Sheet 1 Boundary Scan Order Jtag Instruction Register Options Sheet 2Bypass Register Boundary-Scan Register Vital Product Data VPD ECP ID and Next Pointer Register VPD RegistersVPD ECP VPD Data Register Vital Product Data VPD Address RegisterPage Acronyms Acronyms CSR Index 140

Introduction

Figure 2 shows the 21555 microarchitecture.

Figure 2. 21555 Microarchitecture

215555

ROM

21555 specifications