PCI Bus Transactions

5.2Posted Write Transactions

This section discusses the following Posted Write Transactions:

•Section 5.2.1, “Memory Write Transactions” on page 51.

•Section 5.2.2, “Memory Write and Invalidate Transactions” on page 51.

•Section 5.2.3, “64-bit Extension Posted Write Transaction” on page 52.

•Section 5.2.4, “Write Performance Tuning Options” on page 52.

The 21555 posts all memory write and Memory Write and Invalidate (MWI) transactions that are to be forwarded from one interface to the other. The 21555 accepts write data into its buffers without wait states until one of the following conditions occur:

•The initiator ends the transaction.

•An aligned address boundary is reached.

•The posted write queue fills.

Aligned address disconnect boundaries for memory write and MWI transactions are listed in Section 5.2.1 and Section 5.2.2.

The 21555 does not initiate a memory write transaction on the target bus until at least a cache line amount of data is posted. When the transaction consists of less than a cache line, the 21555 waits until the entire burst is posted. For all posted write behavior dependent on the cache line size (CLS), the 21555 uses the cache line value corresponding to the target interface. For downstream transactions the secondary bus cache line size is used, and for upstream transactions the primary cache line size is used. When the cache line size corresponding to the target bus is not set to a valid value, the 21555 uses a value of 8 Dwords for this purpose. Possible valid values are 8, 16 and 32 Dwords.

Note: A cache line amount of data refers to the number of Dwords only, no address alignment is inferred.

The 21555 continues the transaction to the target as long as write data is available or the transaction has terminated on the initiator bus. Otherwise, the 21555 ends the transaction when a queue-empty condition is detected or when all write data has been delivered for this transaction. The 21555 does not insert master wait states when initiating posted writes.

Note: A queue empty condition occurs when less than a cache line amount of data exists in the posted write buffers. This does not imply any address alignment; in this context cache line refers only to the number of Dwords, and the transaction is not necessarily ended on a cache line boundary.

When the 21555 receives 224 consecutive target retries from the target when attempting to deliver posted write data, the 21555 discards the posted write transaction and conditionally asserts SERR# on the initiator bus (see Chapter 12). This retry counter can be disabled by setting the retry counter disable bit in the Chip Control 0 configuration register. The 21555 also conditionally asserts SERR# on the initiator bus when a target abort or master abort is detected on the target bus in response to the posted write.

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21555 Non-Transparent PCI-to-PCI Bridge User Manual

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Intel 21555 user manual Posted Write Transactions
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21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
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