PCI Bus Transactions

5.4.4.3Read Queue Full Threshold Tuning

The 21555 implements read queue management control bits for each read data queue in the Chip Control 1 configuration register. These bits specify at what read-queue threshold the 21555 initiates a delayed prefetchable read transaction on the target bus. Use of these bits can minimize fragmentation of prefetchable read bursts. The encoding and behavior of these bits are as follows:

•00b: at least eight Dwords free in read data queue for all memory read commands.

•01b: at least eight Dwords free for all memory read commands (same as 00b).

•10b: at least one cache line free for MRL and MRM, eight Dwords free for memory read.

•11b: at least one cache line free for all memory read commands .

In these cases, the initiator bus cache line size is used. When the cache line size is not set to a valid value, 8 Dwords is used for the read queue threshold.

For non-prefetchable memory reads, a threshold of 8 Dwords (one read queue block) is always used.

5.564-Bit and 32-Bit Transactions Initiated by the 21555

The 21555 requests a 64-bit transaction on the primary or secondary bus 64-bit PCI extension by asserting p_req64_l on the primary bus or s_req64_l on the secondary bus, respectively, during the address phase.

The 21555 asserts and deasserts REQ64# during the same cycles in which it asserts and deasserts FRAME#, respectively.

Under the following specific circumstances, the 21555 does not use the 64-bit extension when initiating transactions and therefore does not assert REQ64#:

•Signal p_req64_l was not asserted by the primary bus central function during reset for upstream transactions only. The 64-bit extension is not supported on primary PCI bus.

•The 21555 is initiating an I/O transaction.

•The 21555 is initiating a configuration transaction.

•The 21555 is initiating a nonprefetchable memory read transaction.

•The 21555 is initiating a special cycle transaction.

•The address is not Quadword aligned (AD[2] = 1).

•3 Dwords or less in posted right buffer.

•The 21555 is resuming a memory write transaction after a target disconnect, and ACK64# was not asserted by the target in the previous transaction. (This does not apply when the previous target termination was a target retry.)

•A single Dword read transaction is being performed.

•The address is near the top of a cache line (AD[3] = 1) applies to prefetchable read transactions.

21555 Non-Transparent PCI-to-PCI Bridge User Manual

59

Page 58 Page 60
Page 59
Image 59
Intel 21555 user manual Bit and 32-Bit Transactions Initiated by, Read Queue Full Threshold Tuning
Page 58 Page 60

21555 specifications

The Intel 21555 is a prominent microprocessor developed by Intel, designed to cater to a variety of computing needs. This processor marks a significant step forward in Intel's lineup and underscores the company's commitment to advancing technology in personal computing, enterprise solutions, and beyond.

One of the standout features of the Intel 21555 is its advanced architecture. It utilizes a multi-core design, enabling improved performance through parallel processing. This architecture allows multiple applications to run seamlessly without a decline in speed. The cores are built on a cutting-edge manufacturing process that enhances energy efficiency while maintaining high clock speeds.

The Intel 21555 supports a wide range of technologies, including Intel Turbo Boost, which enables dynamic adjustments to the processor’s performance based on workload demands. This feature allows the processor to accelerate its speed during intensive tasks, providing users with a responsive experience when it matters the most.

Another key characteristic of the Intel 21555 is its support for integrated graphics. With Intel UHD Graphics technology, users can enjoy enhanced visuals for everyday tasks such as video playback, web browsing, and light gaming. This eliminates the need for a separate graphics card for many users, particularly in home office or light gaming scenarios.

Security is a significant focus in the design of the Intel 21555. It includes built-in hardware-based security features like Intel Trusted Execution Technology and Secure Boot. These features help protect against various types of threats, ensuring that user data remains secure from malicious attacks.

The Intel 21555 is also optimized for use with Intel's platform technologies, including Intel Optane memory and Intel Rapid Storage Technology. These technologies work together to deliver faster boot times and improved system responsiveness, making computing more efficient for users.

Furthermore, the Intel 21555 is designed to support virtualization technologies, allowing multiple operating systems to run concurrently without compromising performance. This is particularly useful for developers and businesses that rely on virtualization for testing and development environments.

In summary, the Intel 21555 is a powerful and versatile processor that reflects Intel's ongoing innovation in the computing space. With its multi-core architecture, enhanced graphics capabilities, strong security features, and advanced technologies, it stands out as an excellent choice for a wide range of applications, serving both casual users and professionals alike.
Top Page Image Contents