Intel 21555 user manual Configuration Space Address Register Sheet 4

List of Registers

Table 32. Configuration Space Address Register (Sheet 4 of 5)

Byte		Reset Value		Write	Read
Offset	Register Name		Preload
		(Hex)		Access	Access
(Hex)
	Downstream I/O or Memory 1
C7:C4	and Upstream I/O or Memory 0	00000000	Y	Secondary	Y
	Setup Registers, page 138
	Downstream Memory 0, 2, 3, and
CB:C8	Upstream Memory 1 Setup	00000000	Y	Secondary	Y
	Registers, page 139
	Chip Control 0 Register, page	0y00		[15:11, 9:0]Y
CD:CC		y = 0 or 4	Y	[10]	Y
	156
		(Strapped)		secondary
CF:CE	Chip Control 1 Register, page	0000	Y	Y	Y
	160
D1:D0	Chip Status Register, page 162	0000	—	W1TC	Y
D3:D2	Arbiter Control Register, page	0200	Y	Y	Y
	183
D4	Primary SERR# Disable	00	Y	Y	Y
	Register, page 184
D5	Secondary SERR# Disable	00	Y	Y	Y
	Register, page 184
	Mode Setting Configuration
D7:D6	Register, page 179	0000	—	N	Y
	Determined by Parallel ROM
	Strapping Options
DB:D8	Reset Control Register, page 188	0000	—	Primary	Y
DC	Power Management ECP ID and	01	—	N	Y
	Next Pointer Register, page 185
DD		E4	—	N	N
	Power Management Next Ptr
DF:DE	Power Management Capabilities	0001	Y	Secondary	Y
	Register, page 186
E1:E0	Power Management Control and	0000	Y	Y	Y
	Status Register, page 187
E2	PMCSR Bridge Support	00	—	N	Y
	Extensions, page 187
E3	Power Management Data	00	Y	N	Y
	Register, page 188
E4	Vital Product Data (VPD) ECP ID	04	—	N	Y
	and Next Pointer Register, page
	192
E5	VPD Cap ID	EC	—	N	N
	VPD Next Ptr
	Vital Product Data (VPD)
E7:E6	Address Register, page 193	Indeterminate	—	Y	Y
	VPD Address
EB:E8	VPD Data Register, page 193	Indeterminate	—	Y	Y
	VPD Data

21555 Non-Transparent PCI-to-PCI Bridge User Manual 125