Non-Transparent PCI-to- PCI Bridge
Page
Contents
With SROM, Local, and Host Processors
10.1
Figures
Tables
131
148
108
Page
Brief description of the contents of this manual follows
Preface
Numbering
Data Units
Term Words Bytes Bits
Signal Nomenclature
Signal Type Abbreviations
Signal Description Type
STS
Register Abbreviations
Access Type Description
Register Abbreviations
Introduction
Comparing a 21555 to a Transparent PPB
CPU
Dram PCI ROM
CPU PCI
PPB Feature Comparison
Feature
Architectural Overview
Data Buffers
Registers
Control Logic
Microarchitecture
Special Applications
Programming Notes
Primary Bus VGA Support
Secondary Bus VGA Support
ROM Access
Transaction Forwarding
Page
Signal Pin Functional Groups
Signal Descriptions
Group by Signal Pin Description See
Primary PCI Bus Interface Signals Sheet 1
Primary PCI Bus Interface Signals
Signal Name Type Description
Primary PCI Bus Interface Signals Sheet 2
Ppar
Preql
Pstopl
Primary PCI Bus Interface 64-Bit Extension Signals
Primary PCI Bus Interface 64-Bit Extension Signals Sheet 1
Pack64l
Pad6332
Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2
Ppar64
Preq64l
Pad6332 , pcbel74 , and ppar64 to valid logic levels
Secondary PCI Bus Interface Signals
Secondary PCI Bus Interface Signals Sheet 1
Secondary PCI Bus Interface Signals Sheet 2
Spar
Sstopl
Strdyl
Secondary PCI Bus Interface 64-Bit Extension Signals
Sack64l
Sad6332
Scbel74
Miscellaneous Signals
Miscellaneous Signals
Page
Address Decoding
Expansion ROM Address Mapping Decoding
CSR Address Decoding
Memory 0 Transaction Address Decoding
Using the BAR Setup Registers
BAR Setup Register Example
Direct Address Translation
Address Format
Lookup Table Based Address Translation
Direct Offset Address Translation
Upstream Memory 2 Window Size
Address Translation Using a Lookup Table
Lookup Table Entry Format
Upstream Lookup Table Address Translation
Forwarding of 64-Bit Address Memory Transactions
Lookup Table Entry Format
I/O Transaction Address Decoding
Indirect I/O Transaction Generation
Address Decoding
Type 0 Accesses to 21555 Configuration Space
Configuration Accesses
Subtractive Decoding of I/O Transactions
Initiation of Configuration Transactions by
Address Decoding
Bar Summary
21555 Bar Summary
Bar Size Address Translation
Page
PCI Bus Transactions
Transactions Overview
Posted Write Transactions
Memory Write Transactions
Memory Write and Invalidate Transactions
Write Performance Tuning Options
3 64-bit Extension Posted Write Transaction
Write-Through
Delayed Write Transactions
Delayed Write Transaction Target Termination Returns
Delayed Read Transactions
Target Bus Response Initiator Bus Response
Delayed Read Transaction Target Termination Returns
Nonprefetchable Reads
Read Performance Features and Tuning Options
Prefetchable Read Transactions Using the 64-bit Extension
Prefetchable Reads
Prefetching
Prefetch Boundaries
Read Queue Full Threshold Tuning
64-Bit and 32-Bit Transactions Initiated by
Target Terminations
Target Terminations Returned by
Transaction Termination Errors on the Target Bus
Ordering Rules
Transaction Ordering Rules
PCI Bus Transactions
Page
Power Management, Hot-Swap, and Reset Signals Sheet 1
Power Management, Hot-Swap, and Reset Signals
Initialization Requirements
Reset Behavior
Power Management, Hot-Swap, and Reset Signals Sheet 2
Spmel
Srstinl
Reset Mechanisms
Prstl
Central Function During Reset
21555 Initialization
With SROM, Local, and Host Processors
Without Serial Preload
Power Management Support
Without Local Processor
Without Local Processor and Serial Preload
Without Host Processor
Transitions Between Power Management States
Power Management Actions
Next Power State Action
2 PME# Support
CompactPCI Hot-Swap Functionality
Power Management Data Register
Overview of CompactPCI Controller Hardware Interface
Prstl 332 Ω
Insertion and Removal Process
Primary Lstat K Ω
Initialization Requirements
W Disconnected
W Connected
2a INS ENUM#
4b Insertion
Initialization Requirements
Primary and Secondary PCI Bus Clock Signals
Primary and Secondary PCI Bus Clock Signals Sheet 1
Signal Name Description
Clocking
Primary and Secondary PCI Bus Clock Signals Sheet 2
21555 Secondary Clock Outputs
Sclk
Sclko
66 MHz Support
Page
Interface Signals
Parallel ROM Interface
Prom Interface Signals Sheet 1
Signal Type Description Name
Prom Interface Signals Sheet 2
Prom Read by CSR Access
Parallel and Serial ROM Connection
21555
WE# OE#
Prom Read Timing
Prom Write by CSR Access
Prom Dword Read
Prom Write Timing
Access Time and Strobe Control
Read and Write Strobe Timing
Attaching Additional Devices to the ROM Interface
Attaching Multiple Devices on the ROM Interface
Srom Interface Signals
Srom Interface Signals
Serial ROM Interface
Sromsrom Preload Operation
Srom Configuration Data Preload Format
Srom Operation by CSR Access
Serial ROM Interface
Srom Write All Timing Diagram
Srom Erase Timing Diagram
Page
Primary PCI Bus Arbitration Signals
Secondary PCI Bus Arbitration Signals
Primary PCI Bus Arbitration Signals
Secondary PCI Bus Arbitration Signals
Primary PCI Bus Arbitration
Secondary Bus Arbitration Using the Internal Arbiter
Secondary PCI Bus Arbitration
Secondary Arbiter Example
Arbiter Control Register
Secondary Bus Arbitration Using an External Arbiter
Bit Name Description
Primary and Secondary PCI Bus Interrupt Signals
Primary and Secondary PCI Bus Interrupt Signals
Interrupt and Scratchpad Registers
Interrupt Support
Interrupt and Scratchpad Registers
Doorbell Interrupts
Scratchpad Registers
Page
Error Handling
Error Signals
Primary PCI Bus Error Signals
Primary PCI Bus Error Signals
Secondary PCI Bus Error Signals
Parity Error Responses Sheet 1
Parity Errors
Type PER † Action Taken Error Transaction
Error Transaction
Parity Error Responses Sheet 2
Asserts pperrl
Parity Error Responses Sheet 3
Asserts sperrl
System Error SERR# Reporting
Jtag Signals
Jtag Signals
Jtag Test Port
Test Access Port Controller
Initialization
I2O Support
Inbound Message Passing
I2O Support
Outbound Message Passing
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117
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VPD Support
Reading VPD Information
Writing VPD Information
List of Registers
Register Summary
Register Cross Reference Table
Theory of Operation Chapter Register Reference Information
Configuration Registers
Configuration Space Address Register Sheet 1
Byte Reset Value Write Read
Register Name Preload Hex Access
Configuration Space Address Register Sheet 2
Configuration Space Address Register Sheet 3
Configuration Space Address Register Sheet 4
Configuration Space Address Register Sheet 5
Register Name Reset Value Write Access Read Access
Control and Status Registers
CSR Address Map Sheet 1
CSR Address Map Sheet 2
Ffff W1TS
CSR Address Map Sheet 3
Ffff W1TC
CSR Address Map Sheet 4
Address Decoding
Primary and Secondary Address
CSR Address Map Sheet 5
Primary CSR and Downstream Memory 0 Bara Sheet 1
Primary CSR and Downstream Memory 0 Bara Sheet 2
Secondary CSR Memory BARsa Sheet 1
Primary and Secondary CSR I/O Barsa
Secondary CSR Memory BARsa Sheet 2
Offsets Primary CSR I/O BAR Secondary CSR I/O BAR
Offsets
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR
Upstream I/O or Memory 0 BAR
Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR
Upper 32 Bits Downstream Memory 3 Bar
Upstream Memory 2 Bar
Translated Base
Offsets Downstream I/O or Memory
Xlatbase
Downstream Upstream Offsets Memory Translated Base
Upstream I/O or Memory Setup
139
Configuration Transaction Generation Registers
Upper 32 Bits Downstream Memory 3 Setup Register
Downstream and Upstream Configuration Address Registers
Cfgaddr
Configuration Own Bits Register
Cfgdata
Configuration CSR Sheet 1
Configuration CSR Sheet 2
Downstream I/O Address and Upstream I/O Address Registers
Offset Downstream I/O Address Upstream I/O Address
Ioaddr IA
Downstream I/O Data and Upstream I/O Data Registers
O Own Bits Registers
Offsets Downstream I/O Data Upstream I/O Data
Iodata
Lookup Table Offset Register
O CSR
Lutoffset
Configuration Registers
PCI Registers
Lookup Table Data Register
Upstream Memory 2 Lookup Table
Primary Interface Configuration Space Address Map
Secondary Interface Configuration Space Address Map
Vendor ID Register
Device ID Register
Primary and Secondary Command Registers Sheet 1
Primary and Secondary Command Registers
Offsets Primary Command Secondary Command
Primary and Secondary Command Registers Sheet 2
Primary and Secondary Status Registers Sheet 1
SERR#
Offsets Primary Status Secondary Status
Primary and Secondary Status Registers Sheet 2
Revision ID Rev ID Register
Primary and Secondary Class Code Registers
Primary and Secondary Cache Line Size Registers
Offsets Primary Class Code Secondary Class Code
Offsets Primary Cache Line Size Secondary Cache Line Size
BiST Register
Header Type Register
Offsets Primary MLT Secondary MLT
Subsystem Vendor ID Register
Subsystem ID Register
Enhanced Capabilities Pointer Register
Primary and Secondary Interrupt Line Registers
Primary and Secondary Minimum Grant Registers
Primary and Secondary Interrupt Pin Registers
Primary and Secondary Maximum Latency Registers
Device-Specific Control and Status Address Map
Device-Specific Control and Status Registers
Chip Control 0 Register Sheet 1
Chip Control 0 Register Sheet 2
Chip Control 0 Register Sheet 3
Chip Control 0 Register Sheet 4
Chip Control 1 Register Sheet 1
Chip Control 1 Register Sheet 2
Chip Status Register
Chip Control 1 Register Sheet 3
I20ENA
163
Generic Own Bits Register
Rots
16.6 I2O Registers
I2O Outbound PostList Status
I2O Outbound PostList Interrupt Mask
I2O Inbound PostList Status
I2O Inbound PostList Interrupt Mask
I2O Inbound Queue
I2O Outbound Queue
I2OOUT P
I2O Inbound FreeList Head Pointer
I2O Inbound PostList Tail Pointer
I2O Outbound FreeList Tail Pointer
I2O Outbound PostList Head Pointer
I2O Inbound PostList Counter
I2O Inbound FreeList Counter
Ldipc W1TLS
Ldifc W1TLS
I2O Outbound FreeList Counter
I2O Outbound PostList Counter
Ldopc W1TLS
Interrupt Registers
Chip Status CSR
Chip Set IRQ Mask Register
PMD0 W1TC
Upstream Page Boundary IRQ 0 Register
Chip Clear IRQ Mask Register
PAGE0IRQ W1TC
Upstream Page Boundary IRQ Mask 0 Register
Upstream Page Boundary IRQ 1 Register
Upstream Page Boundary IRQ Mask 1 Register
Primary Clear IRQ and Secondary Clear IRQ Registers
Primary Set IRQ and Secondary Set IRQ Registers
Primary Clear IRQ Secondary Clear IRQ
Primary Set IRQ
Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
Scratchpad 0 Through Scratchpad 7 Registers Sheet 1
Primary Clear IRQ Mask Secondary Clear IRQ Mask
Secondary Set IRQ Mask
Scratchpad 0 Through Scratchpad 7 Registers Sheet 2
Prom Registers
Primary Expansion ROM BAR
Primary Expansion ROM Setup Register
Sequence on
ROM Data Register
ROM Setup Register
Romdata
ROM Control Register Sheet 1
ROM Address Register
Romaddr
Mode Setting Configuration Register Sheet 1
Srom Registers
ROM Control Register Sheet 2
Srompoll
Serial Preload Sequence Sheet 1
Mode Setting Configuration Register Sheet 2
Byte Description Offset
Serial Preload Sequence Sheet 2
Serial Preload Sequence Sheet 3
Error Registers
Arbiter Control
Primary SERR# Disable Register
Secondary SERR# Disable Register
Init Registers
Power Management ECP ID and Next Pointer Register
PM ECP ID
Power Management Capabilities Register
APS
DSI
PME
Power Management Control and Status Register
Pmcsr Bridge Support Extensions
Power Management Data Register
Reset Control Register
CompactPCI Hot-Swap Control Register Sheet 1
HS Next Pointer
CompactPCI Hot-Swap Control Register Sheet 2
Jtag Registers
Jtag Instruction Register Options Sheet 1
Jtag Instruction Register Options Sheet 2
Bypass Register
Boundary-Scan Register
Boundary Scan Order
Vital Product Data VPD ECP ID and Next Pointer Register
VPD Registers
VPD ECP
Vital Product Data VPD Address Register
VPD Data Register
Page
Acronyms
Acronyms
Index
CSR
140
