Non-Transparent PCI-to- PCI Bridge
Page
Contents
With SROM, Local, and Host Processors
10.1
Tables
Figures
131
148
108
Page
Preface
Brief description of the contents of this manual follows
Numbering
Data Units
Term Words Bytes Bits
Signal Type Abbreviations
Signal Nomenclature
Signal Description Type
STS
Register Abbreviations
Access Type Description
Register Abbreviations
Comparing a 21555 to a Transparent PPB
Introduction
CPU
Dram PCI ROM
CPU PCI
Feature
PPB Feature Comparison
Data Buffers
Architectural Overview
Registers
Control Logic
Microarchitecture
Programming Notes
Special Applications
Primary Bus VGA Support
Secondary Bus VGA Support
Transaction Forwarding
ROM Access
Page
Signal Pin Functional Groups
Signal Descriptions
Group by Signal Pin Description See
Primary PCI Bus Interface Signals Sheet 1
Primary PCI Bus Interface Signals
Signal Name Type Description
Ppar
Primary PCI Bus Interface Signals Sheet 2
Preql
Pstopl
Primary PCI Bus Interface 64-Bit Extension Signals Sheet 1
Primary PCI Bus Interface 64-Bit Extension Signals
Pack64l
Pad6332
Ppar64
Primary PCI Bus Interface 64-Bit Extension Signals Sheet 2
Preq64l
Pad6332 , pcbel74 , and ppar64 to valid logic levels
Secondary PCI Bus Interface Signals Sheet 1
Secondary PCI Bus Interface Signals
Spar
Secondary PCI Bus Interface Signals Sheet 2
Sstopl
Strdyl
Sack64l
Secondary PCI Bus Interface 64-Bit Extension Signals
Sad6332
Scbel74
Miscellaneous Signals
Miscellaneous Signals
Page
Address Decoding
Expansion ROM Address Mapping Decoding
CSR Address Decoding
Memory 0 Transaction Address Decoding
BAR Setup Register Example
Using the BAR Setup Registers
Address Format
Direct Address Translation
Direct Offset Address Translation
Lookup Table Based Address Translation
Upstream Memory 2 Window Size
Address Translation Using a Lookup Table
Upstream Lookup Table Address Translation
Lookup Table Entry Format
Lookup Table Entry Format
Forwarding of 64-Bit Address Memory Transactions
Indirect I/O Transaction Generation
I/O Transaction Address Decoding
Address Decoding
Type 0 Accesses to 21555 Configuration Space
Configuration Accesses
Subtractive Decoding of I/O Transactions
Initiation of Configuration Transactions by
Address Decoding
Bar Summary
21555 Bar Summary
Bar Size Address Translation
Page
Transactions Overview
PCI Bus Transactions
Posted Write Transactions
Memory Write and Invalidate Transactions
Memory Write Transactions
3 64-bit Extension Posted Write Transaction
Write Performance Tuning Options
Write-Through
Delayed Write Transactions
Delayed Write Transaction Target Termination Returns
Delayed Read Transactions
Target Bus Response Initiator Bus Response
Nonprefetchable Reads
Delayed Read Transaction Target Termination Returns
Read Performance Features and Tuning Options
Prefetchable Read Transactions Using the 64-bit Extension
Prefetchable Reads
Prefetch Boundaries
Prefetching
64-Bit and 32-Bit Transactions Initiated by
Read Queue Full Threshold Tuning
Target Terminations Returned by
Target Terminations
Ordering Rules
Transaction Termination Errors on the Target Bus
Transaction Ordering Rules
PCI Bus Transactions
Page
Power Management, Hot-Swap, and Reset Signals Sheet 1
Power Management, Hot-Swap, and Reset Signals
Initialization Requirements
Power Management, Hot-Swap, and Reset Signals Sheet 2
Reset Behavior
Spmel
Srstinl
Prstl
Reset Mechanisms
21555 Initialization
Central Function During Reset
Without Serial Preload
With SROM, Local, and Host Processors
Without Local Processor
Power Management Support
Without Local Processor and Serial Preload
Without Host Processor
Power Management Actions
Transitions Between Power Management States
Next Power State Action
2 PME# Support
CompactPCI Hot-Swap Functionality
Power Management Data Register
Overview of CompactPCI Controller Hardware Interface
Prstl 332 Ω
Insertion and Removal Process
Primary Lstat K Ω
Initialization Requirements
W Connected
W Disconnected
2a INS ENUM#
4b Insertion
Initialization Requirements
Primary and Secondary PCI Bus Clock Signals Sheet 1
Primary and Secondary PCI Bus Clock Signals
Signal Name Description
Clocking
21555 Secondary Clock Outputs
Primary and Secondary PCI Bus Clock Signals Sheet 2
Sclk
Sclko
66 MHz Support
Page
Parallel ROM Interface
Interface Signals
Signal Type Description Name
Prom Interface Signals Sheet 1
Prom Interface Signals Sheet 2
Parallel and Serial ROM Connection
Prom Read by CSR Access
21555
WE# OE#
Prom Read Timing
Prom Write by CSR Access
Prom Write Timing
Prom Dword Read
Read and Write Strobe Timing
Access Time and Strobe Control
Attaching Additional Devices to the ROM Interface
Attaching Multiple Devices on the ROM Interface
Srom Interface Signals
Srom Interface Signals
Serial ROM Interface
Sromsrom Preload Operation
Srom Operation by CSR Access
Srom Configuration Data Preload Format
Serial ROM Interface
Srom Write All Timing Diagram
Srom Erase Timing Diagram
Page
Secondary PCI Bus Arbitration Signals
Primary PCI Bus Arbitration Signals
Primary PCI Bus Arbitration Signals
Secondary PCI Bus Arbitration Signals
Primary PCI Bus Arbitration
Secondary Bus Arbitration Using the Internal Arbiter
Secondary PCI Bus Arbitration
Secondary Arbiter Example
Arbiter Control Register
Secondary Bus Arbitration Using an External Arbiter
Bit Name Description
Primary and Secondary PCI Bus Interrupt Signals
Primary and Secondary PCI Bus Interrupt Signals
Interrupt and Scratchpad Registers
Interrupt Support
Interrupt and Scratchpad Registers
Scratchpad Registers
Doorbell Interrupts
Page
Error Signals
Error Handling
Primary PCI Bus Error Signals
Primary PCI Bus Error Signals
Secondary PCI Bus Error Signals
Parity Error Responses Sheet 1
Parity Errors
Type PER † Action Taken Error Transaction
Error Transaction
Parity Error Responses Sheet 2
Asserts pperrl
Asserts sperrl
Parity Error Responses Sheet 3
System Error SERR# Reporting
Jtag Signals
Jtag Signals
Jtag Test Port
Initialization
Test Access Port Controller
Inbound Message Passing
I2O Support
I2O Support
Outbound Message Passing
116
117
Page
Reading VPD Information
VPD Support
Writing VPD Information
Register Summary
List of Registers
Register Cross Reference Table
Theory of Operation Chapter Register Reference Information
Configuration Space Address Register Sheet 1
Configuration Registers
Byte Reset Value Write Read
Register Name Preload Hex Access
Configuration Space Address Register Sheet 2
Configuration Space Address Register Sheet 3
Configuration Space Address Register Sheet 4
Register Name Reset Value Write Access Read Access
Configuration Space Address Register Sheet 5
Control and Status Registers
CSR Address Map Sheet 1
CSR Address Map Sheet 2
Ffff W1TS
CSR Address Map Sheet 3
Ffff W1TC
CSR Address Map Sheet 4
Primary and Secondary Address
Address Decoding
CSR Address Map Sheet 5
Primary CSR and Downstream Memory 0 Bara Sheet 1
Secondary CSR Memory BARsa Sheet 1
Primary CSR and Downstream Memory 0 Bara Sheet 2
Primary and Secondary CSR I/O Barsa
Secondary CSR Memory BARsa Sheet 2
Offsets Primary CSR I/O BAR Secondary CSR I/O BAR
Offsets
Downstream I/O or Memory 1 and Upstream I/O or Memory 0 BAR
Upstream I/O or Memory 0 BAR
Downstream Memory 2 and 3 BAR, and Upstream Memory 1 BAR
Upstream Memory 2 Bar
Upper 32 Bits Downstream Memory 3 Bar
Translated Base
Offsets Downstream I/O or Memory
Xlatbase
Downstream Upstream Offsets Memory Translated Base
Upstream I/O or Memory Setup
139
Upper 32 Bits Downstream Memory 3 Setup Register
Configuration Transaction Generation Registers
Cfgaddr
Downstream and Upstream Configuration Address Registers
Cfgdata
Configuration Own Bits Register
Configuration CSR Sheet 1
Downstream I/O Address and Upstream I/O Address Registers
Configuration CSR Sheet 2
Offset Downstream I/O Address Upstream I/O Address
Ioaddr IA
O Own Bits Registers
Downstream I/O Data and Upstream I/O Data Registers
Offsets Downstream I/O Data Upstream I/O Data
Iodata
Lookup Table Offset Register
O CSR
Lutoffset
PCI Registers
Configuration Registers
Lookup Table Data Register
Upstream Memory 2 Lookup Table
Secondary Interface Configuration Space Address Map
Primary Interface Configuration Space Address Map
Vendor ID Register
Device ID Register
Primary and Secondary Command Registers Sheet 1
Primary and Secondary Command Registers
Offsets Primary Command Secondary Command
Primary and Secondary Status Registers Sheet 1
Primary and Secondary Command Registers Sheet 2
SERR#
Offsets Primary Status Secondary Status
Revision ID Rev ID Register
Primary and Secondary Status Registers Sheet 2
Primary and Secondary Cache Line Size Registers
Primary and Secondary Class Code Registers
Offsets Primary Class Code Secondary Class Code
Offsets Primary Cache Line Size Secondary Cache Line Size
BiST Register
Header Type Register
Offsets Primary MLT Secondary MLT
Subsystem ID Register
Subsystem Vendor ID Register
Enhanced Capabilities Pointer Register
Primary and Secondary Interrupt Line Registers
Primary and Secondary Minimum Grant Registers
Primary and Secondary Interrupt Pin Registers
Primary and Secondary Maximum Latency Registers
Device-Specific Control and Status Address Map
Device-Specific Control and Status Registers
Chip Control 0 Register Sheet 1
Chip Control 0 Register Sheet 2
Chip Control 0 Register Sheet 3
Chip Control 0 Register Sheet 4
Chip Control 1 Register Sheet 1
Chip Control 1 Register Sheet 2
Chip Status Register
Chip Control 1 Register Sheet 3
I20ENA
163
Rots
Generic Own Bits Register
I2O Outbound PostList Status
16.6 I2O Registers
I2O Outbound PostList Interrupt Mask
I2O Inbound PostList Status
I2O Inbound Queue
I2O Inbound PostList Interrupt Mask
I2O Outbound Queue
I2OOUT P
I2O Inbound PostList Tail Pointer
I2O Inbound FreeList Head Pointer
I2O Outbound FreeList Tail Pointer
I2O Outbound PostList Head Pointer
I2O Inbound FreeList Counter
I2O Inbound PostList Counter
Ldipc W1TLS
Ldifc W1TLS
I2O Outbound FreeList Counter
I2O Outbound PostList Counter
Ldopc W1TLS
Chip Status CSR
Interrupt Registers
Chip Set IRQ Mask Register
PMD0 W1TC
Upstream Page Boundary IRQ 0 Register
Chip Clear IRQ Mask Register
PAGE0IRQ W1TC
Upstream Page Boundary IRQ Mask 0 Register
Upstream Page Boundary IRQ 1 Register
Upstream Page Boundary IRQ Mask 1 Register
Primary Set IRQ and Secondary Set IRQ Registers
Primary Clear IRQ and Secondary Clear IRQ Registers
Primary Clear IRQ Secondary Clear IRQ
Primary Set IRQ
Scratchpad 0 Through Scratchpad 7 Registers Sheet 1
Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
Primary Clear IRQ Mask Secondary Clear IRQ Mask
Secondary Set IRQ Mask
Scratchpad 0 Through Scratchpad 7 Registers Sheet 2
Prom Registers
Primary Expansion ROM BAR
Sequence on
Primary Expansion ROM Setup Register
ROM Data Register
ROM Setup Register
Romdata
ROM Control Register Sheet 1
ROM Address Register
Romaddr
Srom Registers
Mode Setting Configuration Register Sheet 1
ROM Control Register Sheet 2
Srompoll
Serial Preload Sequence Sheet 1
Mode Setting Configuration Register Sheet 2
Byte Description Offset
Serial Preload Sequence Sheet 2
Serial Preload Sequence Sheet 3
Arbiter Control
Error Registers
Secondary SERR# Disable Register
Primary SERR# Disable Register
Init Registers
Power Management ECP ID and Next Pointer Register
PM ECP ID
APS
Power Management Capabilities Register
DSI
PME
Pmcsr Bridge Support Extensions
Power Management Control and Status Register
Reset Control Register
Power Management Data Register
HS Next Pointer
CompactPCI Hot-Swap Control Register Sheet 1
CompactPCI Hot-Swap Control Register Sheet 2
Jtag Registers
Jtag Instruction Register Options Sheet 1
Bypass Register
Jtag Instruction Register Options Sheet 2
Boundary-Scan Register
Boundary Scan Order
Vital Product Data VPD ECP ID and Next Pointer Register
VPD Registers
VPD ECP
VPD Data Register
Vital Product Data VPD Address Register
Page
Acronyms
Acronyms
CSR
Index
140
