Intel 21555 Primary and Secondary Status Registers Sheet 2, Revision ID Rev ID Register

List of Registers

Table 62. Primary and Secondary Status Registers (Sheet 2 of 2)

The bits described in Table 62 reflect the status of the 21555 primary interface for the Primary Status register, and of the secondary interface for the Secondary Status register. W1TC indicates that writing a 1 to that bit clears the bit to 0. Writing a 0 has no effect.

Offsets			Primary Status	Secondary Status
Primary byte			07:06h	47:46h
Secondary byte			47:46h	07:06h
Bit	Name	R/W	Description
			This bit is set to a 1 when all of the following are true:
			• The 21555 is a master on the corresponding bus.
8	Data Parity	R/	• PERR# is detected asserted for writes or a parity error is detected
			for reads.
	Detected	W1TC

•Parity Error Response bit is set in the Primary or Secondary Command register.

			Reset value is 0.
			Indicates slowest response to a non configuration command on the
10:9	DEVSEL# timing	R	corresponding interface. Reads as 01b to indicate that the 21555
			responds no slower than with medium timing.
	Signaled Target	R/	This bit is set to a 1 when the 21555 is acting as a target on the
11			corresponding bus and returns a target abort to the initiator.
	Abort	W1TC
			Reset value is 0.
	Received Target	R/	This bit is set to a 1 when the 21555 is acting as an initiator on the
12			corresponding bus and receives a target abort.
	Abort	W1TC
			Reset value is 0.
	Received Master	R/	This bit is set to a 1 when the 21555 is acting as an initiator on the
13			corresponding bus and detects a master abort.
	Abort	W1TC
			Reset value is 0.
	Signaled System	R/	This bit is set to a 1 when the 21555 has asserted SERR# on the
14			corresponding bus.
	Error	W1TC
			Reset value is 0.
	Detected Parity	R/	This bit is set to a 1 when the 21555 detects an address or data parity
15			error on the corresponding interface.
	Error	W1TC
			Reset value is 0.

Table 63. Revision ID (Rev ID) Register

• Primary byte offset: 08h and 48h

• Secondary byte offset: 08h and 48h

Bit	Name	R/W	Description
7:0	Revision ID	R	This register indicates the revision number of this device. The initial revision
			reads as 0. Subsequent revisions increment by 1.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 151