Intel 21555 user manual Error Handling, Primary PCI Bus Error Signals

Error Handling 12

This chapter presents the theory of operation information about the 21555 Error handling capability. See Chapter 16 for specific information about the Error registers.

12.1Error Signals

This section describes both the primary and secondary PCI bus error signals.

12.1.1Primary PCI Bus Error Signals

Table 27 describes the primary PCI bus error signals.

Table 27. Primary PCI Bus Error Signals

Signal Name	Type	Description
		Primary PCI interface PERR#. Signal p_perr_l is asserted when a data parity error is
		detected for data received on the primary interface. The timing of p_perr_l
		corresponds to p_par driven one clock cycle earlier, and p_ad and p_cbe_l driven
p_perr_l	STS	two clock cycles earlier. Signal p_perr_l is asserted by the target during write
		transactions, and by the initiator during read transactions.
		Upon completion of a transaction, p_perr_l is driven to a deasserted state for one
		clock cycle and is then sustained by an external pull-up resistor.
		Primary PCI interface SERR#. Signal p_serr_l can be driven low by any device on
		the primary bus to indicate a system error condition. The 21555 can conditionally
		assert p_serr_l for the following reasons:
		• Primary bus address parity error.
		• Downstream posted write data parity error on secondary bus.
		• Master abort during downstream posted write transaction.
p_serr_l	OD	• Target abort during downstream posted write transaction.
		• Downstream posted write transaction discarded.
		• Downstream delayed write request discarded.
		• Downstream delayed read request discarded.
		• Downstream delayed transaction master timeout.
		• Secondary bus s_serr_l assertion.
		Signal p_serr_l is pulled up through an external resistor.

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