Intel 21555 user manual Parity Error Responses Sheet 2, Error Transaction, Asserts pperrl

Error Handling

Table 29. Parity Error Responses (Sheet 2 of 3)

Type of	Type of	PER†	Action Taken
Error	Transaction	PS

•Queues and forwards transaction with parity error.

0 —

•Sets primary Parity Error Detected bit.

	Downstream		•	Returns TRDY# (and STOP# when multiple data phases
	Delayed			requested).
	Write	1 —	•	Transaction not forwarded.
			• Sets primary Parity Error Detected bit.
			•	Asserts p_perr_l.
		0 —	•	Transaction completes normally on primary bus.
		1 —	• Transaction completes normally on primary bus.
	Upstream		•	Sets primary Data Parity Detected bit when p_perr_l is asserted.
	Delayed
			• Transaction completes normally on primary bus.
	Write
			• Sets primary Data Parity Detected bit when p_perr_l is asserted.
		1 1
			• Asserts s_perr_l when returning s_trdy_l to initiator on secondary
				bus (for both CSR and BAR forwarding mechanisms).
Data Parity
	Downstream	—
Error on	Delayed		The 21555 is returning data, all action is taken by initiator.
		—
Primary	Read
Bus
			• Returns read data with bad parity to initiator (for both CSR and BAR
		0 —		forwarding mechanisms).
			• Sets primary Parity Error Detected bit.
	Upstream
			• Returns read data with bad parity to initiator (for both CSR and BAR
	Delayed
				forwarding mechanisms).
	Read
			•	Sets primary Parity Error Detected bit.
		1 —
			• Sets primary Data Parity Detected bit.
			•	Asserts p_perr_l.
		0 —	• Writes the data normally.
			• Sets the primary Parity Error Detected bit.
	Configuration
	Register or		•	Writes the data normally.
	CSR Write	1 —	•	Sets the primary Parity Error Detected bit.
			•	Asserts p_perr_l.
	Configuration	—
	Register or		Returns read data normally.
		—
	CSR Read

†PER: Parity Error Response bit (Primary Secondary).

108 21555 Non-Transparent PCI-to-PCI Bridge User Manual