Intel 21555 user manual Primary SERR# Disable Register, Secondary SERR# Disable Register

List of Registers

Table 116. Primary SERR# Disable Register

This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert p_serr_l for a particular condition. When the bit is a 0, the assertion of p_serr_l is not masked for this event.

When the bit is a 1, the assertion of p_serr_l is masked for this event.

•Primary byte offset: D4h

•Secondary byte offset: D4h

Bit	Name	R/W	Description
	Downstream		Disables p_serr_l assertion when a downstream master time-out condition
	Delayed
0	Transaction	R/W	is detected and the downstream transaction is discarded.
	Master		Reset value is 0
	Time-out
	Downstream		Disables p_serr_l assertion when 21555 discards a downstream delayed
1	Delayed Read	R/W	read transaction request after receiving 224 target retries from secondary bus
	Transaction		target.
	Discarded		Reset value is 0
	Downstream		Disables p_serr_l assertion when 21555 discards a downstream delayed
2	Delayed Write	R/W	write transaction request after receiving 224 target retries from secondary
	Transaction		bus target.
	Discarded		Reset value is 0
	Downstream		Disables p_serr_l assertion when 21555 discards a downstream posted
3	Posted Write	R/W	write transaction after receiving 224 target retries from secondary bus target.
	Data Discarded		Reset value is 0
	Target Abort		Disables p_serr_l assertion when 21555 detects a target abort on the
	during
4		R/W	secondary interface in response to a downstream posted write.
	Downstream
			Reset value is 0
	Posted Write
	Master Abort		Disables p_serr_l assertion when the 21555 detects a master abort on the
	during
5		R/W	secondary interface when initiating a downstream posted write.
	Downstream
			Reset value is 0
	Posted Write
	Downstream		Disables p_serr_l assertion when the 21555 detects s_perr_l asserted
6	Posted Write	R/W	during a downstream posted write.
	Parity Error		Reset value is 0
7	Reserved	R	Reserved. Returns 0 when read.

Table 117. Secondary SERR# Disable Register

This register may be preloaded by serial ROM or programmed by the local processor before host configuration. This register controls the ability of the 21555 to assert s_serr_l for a particular condition. When the bit is a 0, the assertion of s_serr_l is not masked for this event.

When the bit is a 1, the assertion of s_serr_l is masked for this event.

•Primary byte offset: D5h

•Secondary byte offset: D5h

Bit	Name	R/W	Description
	Upstream Delayed		Disables s_serr_l assertion when an upstream master timeout
0	Transaction Master	R/W	condition is detected and the upstream transaction is discarded.
	Timeout		Reset value is 0

184 21555 Non-Transparent PCI-to-PCI Bridge User Manual