Intel 21555 user manual ROM Setup Register, ROM Data Register, Romdata

List of Registers

Table 109. ROM Setup Register

Byte Offsets: 0C9:0C8h

Bit	Name	R/W	Description
			Number of p_clk cycles that pr_cs_l asserts low (in default mode) or
			pr_ale_l drives high (in multiple device mode) for a PROM or other external
			device access. Possible values:
			• 00: 8 times 33 MHz p_clk cycle time
			00:16 times 66 MHz p_clk cycle time
			• 01: 16 times 33 MHz p_clk cycle time
1:0	Access Time	R/W	01: 32 times 66 MHz p_clk cycle time
			• 10: 64 times 33 MHz p_clk cycle time
			10:128 times 66 MHz p_clk cycle time
			• 11: 256 times 33 MHz p_clk cycle time
			11:512 times 66 MHz p_clk cycle time
			A 33 MHz p_clk is specified by p_m66ena low, and a 66 MHz p_clk is
			specified by p_m66ena high.
			Reset value is 00b
7:2	Reserved	R	Reserved. Reads only as 0.
			Read and write strobe timing mask. This 8-bit field defines the setup time,
			duration, and hold time of pr_rd_l and pr_wr_l during the device select
			assertion. A 1 asserts the strobe, a 0 deasserts it. The LSB is the first bit in
			time, the MSB is the last bit. Each bit is one eighth of the access time, or for
			the following access time values:
			• 00: 1 each 33 MHz or 2 each 66 MHz p_clk cycles per bit
15:8	Strobe Mask	R/W	• 01: 2 each 33 MHz or 4 each 66 MHz p_clk cycles per bit
			• 10: 8 each 33 MHz or 16 each 66 MHz p_clk cycles per bit
			• 11: 32 each 33 MHz or 64 each 66 MHz p_clk cycles per bit
			A 33 MHz p_clk is specified by p_m66ena low, and a 66 MHz p_clk is
			specified by p_m66ena high.
			Reset value is 01111110b

Table 110. ROM Data Register

Byte Offsets: 0CAh

Bit	Name	R/W	Description
			• When the PROM Start bit is set, contains the read or write
7:0	ROM_DATA	R/W	data for bits [7:0] of the PROM.
			• When the Serial ROM Start bit is set, contains the read or
			write data for bits [7:0] of the serial ROM.

21555 Non-Transparent PCI-to-PCI Bridge User Manual 177