Intel 21555 user manual Configuration CSR Sheet 1

List of Registers

Table 48. Configuration Own Bits Register

7:1	Reserved	R	Read only as 0.
			Indicates ownership of the Upstream Configuration Address and
			Upstream Configuration Data registers.
			• When 0, upstream Configuration Address and Upstream
			Configuration Data registers are not owned. When read as a 0
			from the secondary interface, this bit is subsequently set to a 1 by
	Upstream	R0TS (S)	the 21555 if the Upstream Configuration Control bit is a 1.
8	Configuration		• When 1, a master owns Upstream Configuration Address and
		R(P)
	Own Bit		Upstream Configuration Data registers. When this semaphore
			method is used, other masters should not attempt to access
			these registers when this bit is a 1. This bit is automatically
			cleared once the configuration transaction has completed on the
			initiator bus.
			• Reset value is 0.
15:9	Reserved	R	Read only as 0.

Table 49. Configuration CSR (Sheet 1 of 2)

This register is also mapped in memory and I/O space.

• Primary byte offset: 93:92h

• Secondary byte offset: 93:92h

• CSR byte offset: 013:012h

Bit	Name	R/W	Description
	Downstream		Provides the current value of the Downstream Configuration Own bit. This
0	Configuration	R
			bit has no side effects when read.
	Own Status
			Enables the 21555 to perform downstream indirect configuration
			transactions.
			• When 0, the 21555 will not initiate a configuration transaction on the
	Downstream		secondary interface when the Downstream Configuration Data
			register is accessed. The Downstream Configuration Data register is
1	Configuration	R/W
			treated as a reserved register.
	Control
			• When 1, the 21555 is enabled to perform downstream configuration
			transactions when the Downstream Configuration Data register is
			accessed.
			• Reset value is 0
			Controls the 21555 ability to respond to a configuration transaction that it
			generates as a master.
	Downstream		• When 0, the 21555 does not respond to configuration transactions
2	Self-Response	R/W	that it generates.
	Enable		• When 1, the 21555 does not respond to configuration transactions
			that it generates as a master.
			• Reset value is 0
7:3	Reserved	R	Reserved. Returns 0 when read.
	Upstream		Provides the current value of the Upstream Configuration Own bit. This bit
8	Configuration	R
			has no side effects when read.
	Own Status

21555 Non-Transparent PCI-to-PCI Bridge User Manual 143