Integer Divide Idiv, Idivu | Xilinx EDK 8.2i specification

Instructions

idiv	Integer Divide
	idiv	rD, rA, rB	divide rB by rA (signed)
	idivu	rD, rA, rB	divide rB by rA (unsigned)

R

0 1 0 0 1 0

rD

rA

rB

0 0 0 0 0 0 0 0 0 U 0

0

6

11

16

21

31

Description

The contents of register rB is divided by the contents of register rA and the result is placed into register rD.

If the U bit is set, rA and rB is considered unsigned values. If the U bit is clear, rA and rB is considered signed values

If the value of rA is 0, the divide_by_zero bit in MSR will be set and the value in rD will be 0.

Pseudocode

if (rA) = 0then (rD) ← 0

else

(rD) ← (rB) / (rA)

Registers Altered

•rD, unless “Divide by zero” exception is generated, in which case the register is unchanged

•MSR[Divide_By_Zero]

Latency

1 cycle if (rA) = 0, otherwise 32 cycles

Note

This instruction is only valid if MicroBlaze is conﬁgured to use a hardware divider (C_USE_DIV = 1).

MicroBlaze Processor Reference Guide	www.xilinx.com	107
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 107

Xilinx EDK 8.2i manual Integer Divide Idiv, Idivu

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness FSR MSRESR EAR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PC PVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name Description FSL EIPDCE ICE Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusediv CFGCusebarrel DIV Cunalignedexception CdebugenabledOP0EXEC Unexec Ccachebytesize IcllCicachelinelen Icbs Rstmsr CresetmsrPipeline Architecture Arch Branches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Exception Causes ResetHardware Exceptions Equivalent Pseudocode Hardware Breaks Breaks Latency InterruptUser Vector Exception Software Breaks Instruction Cache Instruction CacheOverview General Instruction Cache Functionality MSR Bit Data CacheInstruction Cache Operation Instruction Cache Software Support Data Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Arithmetic FormatRounding Operations Comparison Hardware Acceleration using FSLFast Simplex Link FSL Exceptions Trace Overview Debug and TraceDebug Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb Ixcl Dmrnw Dopb MicroBlaze Signal Interface Description Mfsl Imrnw IopbDAS Dlmb IAS Ilmb Dxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxcls Addr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface Description DataRead031 DataWrite031ReadStrobe WriteStrobe Generic Read Operation LMB TransactionsGeneric Write Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write Operation CacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss MDM Debug Interface DescriptionTrace Interface Description Debug Interface Description MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne Cunalignedexception Cdcacheusefsl FfffCicacheusefsl Data Types Scope 2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type B Registers Altered AddDescription Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Andn RD, rA, rB AndnLogical and not Logical and not with Immediate Andni RD, rA, IMM Andni Beqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Branch if Less Than Blt Blt Bltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Brad Instructions Unconditional BranchBra Brd MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Bsll Instructions Barrel Shift BsrlBsra Bslli BsiBarrel Shift Immediate Bsrli Bsrai Cmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Floating Point Arithmetic Multiplication Fmul Fmul Esrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB Divide Fcmp Esrec FSRIO,DO Cget GetGet from fsl interface Nget Idivu IdivInteger Divide Idiv Immediate ImmIMM Imm Lbu RD, rA, rB LbuLoad Byte Unsigned Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Cput PutPut to fsl interface Nput Rsubk RsubArithmetic Reverse Subtract Rsub Rsubc Rsubik RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubic Rtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Srl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Xori RA, rD, IMM XoriLogical Exclusive or with Immediate 148