Xilinx EDK 8.2i manual Interrupt, User Vector Exception, Software Breaks, Latency, Pseudocode

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Chapter 1: MicroBlaze Architecture

Software Breaks

To perform a software break, use the brk and brki instructions. Refer to Chapter 4, “MicroBlaze Instruction Set Architecture” for detailed information on software breaks.

Latency

The time it will take MicroBlaze to enter a break service routine from the time the break occurs, depends on the instruction currently in the execution stage and the latency to the memory storing the break vector.

Equivalent Pseudocode

r16 ← PC

PC ← 0x00000018 MSR[BIP] ← 1

Interrupt

MicroBlaze supports one external interrupt source (connecting to the Interrupt input port). The processor will only react to interrupts if the Interrupt Enable (IE) bit in the Machine Status Register (MSR) is set to 1. On an interrupt the instruction in the execution stage will complete, while the instruction in the decode stage is replaced by a branch to the interrupt vector (address 0x10). The interrupt return address (the PC associated with the instruction in the decode stage at the time of the interrupt) is automatically loaded into general purpose register R14. In addition, the processor also disables future interrupts by clearing the IE bit in the MSR. The IE bit is automatically set again when executing the RTID instruction.

Interrupts are ignored by the processor if either of the break in progress (BIP) or exception in progress (EIP) bits in the MSR are set to 1.

Latency

The time it will take MicroBlaze to enter an Interrupt Service Routine (ISR) from the time an interrupt occurs depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors. If MicroBlaze is configured to have a hardware divider, the largest latency will happen when an interrupt occurs during the execution of a division instruction.

Equivalent Pseudocode

r14 ← PC

PC ← 0x00000010 MSR[IE] ← 0

User Vector (Exception)

The user exception vector is located at address 0x8. A user exception is caused by inserting a ‘BRALID Rx,0x8’ instruction in the software flow. Although Rx could be any general purpose register Xilinx recommends using R15 for storing the user exception return address, and to use the RTSD instruction to return from the user exception handler.

Pseudocode

rx ← PC

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