Registers Altered | Xilinx EDK 8.2i specification

Instructions

sh	Store Halfword
	sh	rD, rA, rB

R

1 1 0 1 0 1

rD

rA

rB

0 0 0 0 0 0 0 0 0 0 0

0

6

11

16

21

31

Description

Stores the contents of the least signiﬁcant halfword of register rD, into the halfword aligned memory location that results from adding the contents of registers rA and rB.

Pseudocode

Addr ← (rA) + (rB)

Addr[31] ← 0

Mem(Addr) ← (rD)[16:31]

Registers Altered

•ESR [S]

Latency

1 cycle

MicroBlaze Processor Reference Guide	www.xilinx.com	137
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 137

Xilinx EDK 8.2i manual Registers Altered, Instructions Store Halfword RD, rA, rB

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness ESR MSREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Special Purpose Registers General Purpose RegistersProgram Counter PC Registers Machine Status Register MSR 8Program Counter PC Bits Name Description Reset Value9Machine Status Register MSR Bits Name Description PVR DCE EIPICE FSL Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusebarrel CFGDIV Cusediv OP0EXEC CdebugenabledUnexec Cunalignedexception Cicachelinelen IcllIcbs Ccachebytesize Pipeline Architecture CresetmsrArch Rstmsr Branches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Hardware Exceptions ResetEquivalent Pseudocode Exception Causes Hardware Breaks Breaks User Vector Exception InterruptSoftware Breaks Latency Overview Instruction CacheGeneral Instruction Cache Functionality Instruction Cache Instruction Cache Operation Data CacheInstruction Cache Software Support MSR Bit Data Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Rounding FormatOperations Arithmetic Fast Simplex Link FSL Hardware Acceleration using FSLExceptions Comparison Trace Overview Debug and TraceDebug Overview MicroBlaze Architecture Ilmb MicroBlaze I/O OverviewIxcl Dxcl Dmrnw Dopb MicroBlaze Signal Interface Description DAS Dlmb Imrnw IopbIAS Ilmb Mfsl Ixclm On-Chip Peripheral Bus OPB Interface DescriptionDxcls Dxclm ByteEnable03 LMB Signal InterfaceLocal Memory Bus LMB Interface Description Addr031 ReadStrobe DataWrite031WriteStrobe DataRead031 Generic Read Operation LMB TransactionsGeneric Write Operation Single Cycle Back-to-Back Read Operation Back-to-Back Write OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL Transactions Xilinx CacheLink XCL Interface DescriptionFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Trace Interface Description Debug Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cusemsrinstr CusepcmpinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Cdcacheusefsl FfffCicacheusefsl Data Types Scope 2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Type a FormatsType B Opcode Destination Reg Source Reg a Immediate Value Registers Altered AddDescription Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Andn RD, rA, rB AndnLogical and not Logical and not with Immediate Andni RD, rA, IMM Andni Beqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Branch if Less Than Blt Blt Bltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Bra Instructions Unconditional BranchBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Bsll Instructions Barrel Shift BsrlBsra Barrel Shift Immediate Bsrli BsiBsrai Bslli Cmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Floating Point Arithmetic Multiplication Fmul Fmul Floating Point Arithmetic Division FdivFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get from fsl interface GetNget Cget Idivu IdivInteger Divide Idiv Immediate ImmIMM Imm Lbu RD, rA, rB LbuLoad Byte Unsigned Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Put to fsl interface PutNput Cput Arithmetic Reverse Subtract Rsub RsubRsubc Rsubk Arithmetic Reverse Subtract Immediate Rsubi RsubiRsubic Rsubik Rtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Srl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Xori RA, rD, IMM XoriLogical Exclusive or with Immediate 148