Xilinx CacheLink XCL Interface Description

Xilinx CacheLink (XCL) Interface Description

FSL Transactions

FSL BUS Write Operation

A write to the FSL bus is performed by MicroBlaze using one of the ﬂavors of the put instruction. A write operations transfers the register contents to an output FSL bus. The transfer is completed in a single clock cycle for blocking mode writes to the FSL (put and cput instructions) as long as the FSL FIFO does not become full. If the FSL FIFO is full, the processor stalls until the FSL full ﬂag is lowered. The non-blocking instructions: nput and ncput, will always complete in a single clock cycle even if the FSL was full. If the FSL was full, the write is inhibited and the carry bit is set in the MSR.

FSL BUS Read Operation

A read from the FSL bus is performed by MicroBlaze using one of the ﬂavors of the get instruction. A read operations transfers the contents of an input FSL to a general purpose register. The transfer is typically completed in 2 clock cycles for blocking mode reads from the FSL (get and cget instructions) as long as data exists in the FSL FIFO. If the FSL FIFO is empty, the processor stalls at this instruction until the FSL exists ﬂag is set. In the non- blocking mode (nget and ncget instructions), the transfer is completed in two clock cycles irrespective of whether or not the FSL was empty. In the case the FSL was empty, the transfer of data does not take place and the carry bit is set in the MSR.