Lhu RD, rA, rB | Xilinx EDK 8.2i instruction

Instructions

lhu	Load Halfword Unsigned
	lhu	rD, rA, rB

R

1 1 0 0 0 1

rD

rA

rB

0 0 0 0 0 0 0 0 0 0 0

0

6

11

16

21

31

Description

Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of registers rA and rB. The data is placed in the least signiﬁcant halfword of register rD and the most signiﬁcant halfword in rD is cleared.

Pseudocode

Addr ← (rA) + (rB) Addr[31] ← 0 (rD)[16:31] ← Mem(Addr) (rD)[0:15] ← 0

Registers Altered

•rD, unless unaligned data access exception is generated, in which case the register is unchanged.

•ESR [W]

Latency

1 cycle

MicroBlaze Processor Reference Guide	www.xilinx.com	111
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 111

Xilinx EDK 8.2i manual Lhu RD, rA, rB

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness FSR MSRESR EAR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PC PVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name Description FSL EIPDCE ICE Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusediv CFGCusebarrel DIV Cunalignedexception CdebugenabledOP0EXEC Unexec Ccachebytesize IcllCicachelinelen Icbs Rstmsr CresetmsrPipeline Architecture Arch Delay Slots Memory ArchitectureBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Exception Causes ResetHardware Exceptions Equivalent Pseudocode Hardware Breaks Breaks Latency InterruptUser Vector Exception Software Breaks Instruction Cache Instruction CacheOverview General Instruction Cache Functionality MSR Bit Data CacheInstruction Cache Operation Instruction Cache Software Support General Data Cache Functionality Data Cache OperationData Cache Floating Point Unit FPU Data Cache Software SupportWDC Instruction Arithmetic FormatRounding Operations Comparison Hardware Acceleration using FSLFast Simplex Link FSL Exceptions Debug and Trace Debug OverviewTrace Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb Ixcl Dmrnw Dopb MicroBlaze Signal Interface Description Mfsl Imrnw IopbDAS Dlmb IAS Ilmb Dxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxcls Addr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface Description DataRead031 DataWrite031ReadStrobe WriteStrobe LMB Transactions Generic Write OperationGeneric Read Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation Read and Write Data Steering RD1623 RD2431RD07 RD815 RD1623 RD2431 Master FSL Signal Interface Slave FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write Operation CacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read MissData Cache Write MDM Debug Interface DescriptionTrace Interface Description Debug Interface Description MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne Cunalignedexception Ffff CicacheusefslCdcacheusefsl Data Types Scope Register Usage Conventions MicroBlaze Application Binary Interface2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling 1Symbol notation Meaning SummaryNotation Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type B Add DescriptionRegisters Altered Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Andn Logical and notAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM Andni Beq Branch if Equal BeqBeqd Beqi Branch Immediate if Equal BeqiBeqid Bge Branch if Greater or Equal BgeBged Bgei Branch Immediate if Greater or Equal BgeiBgeid Bgt Branch if Greater Than BgtBgtd Bgti Branch Immediate if Greater Than BgtiBgtid Ble Branch if Less or Equal BleBled Blei Branch Immediate if Less or Equal BleiBleid Branch if Less Than Blt Blt Blti BltiBltid Bne Branch if Not Equal BneBned Bnei Branch Immediate if Not Equal BneiBneid Brad Instructions Unconditional BranchBra Brd MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Instructions Barrel Shift Bsrl BsraBsll Bslli BsiBarrel Shift Immediate Bsrli Bsrai Cmp Integer Compare CmpCmpu Fadd Floating Point Arithmetic Add FaddEsrec FSRIO,UF,OF,DO Frsub Reverse Floating Point Arithmetic SubtractionFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul Fmul Esrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB Divide Fcmp Esrec FSRIO,DO Cget GetGet from fsl interface Nget Idiv Integer Divide IdivIdivu Immediate ImmIMM Imm Lbu Load Byte UnsignedLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Cput PutPut to fsl interface Nput Rsubk RsubArithmetic Reverse Subtract Rsub Rsubc Rsubik RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubic Rtbd Return from BreakRtbd RA, IMM Rtid Return from Interrupt Rtid RA, IMMMsrie Rted Return from Exception Rted RA, IMMMsree Msreip ESR Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sext8 Sign Extend ByteSext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Srl Shift Right LogicalSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Xori Logical Exclusive or with ImmediateXori RA, rD, IMM 148