Manuals / Xilinx / Computer Equipment / Typewriter

Xilinx EDK 8.2i manual Manual Contents, Additional Resources

Models: EDK 8.2i

1 148

Download 148 pages 28.91 Kb

Page 7

R

Preface

About This Guide

Welcome to the MicroBlaze Processor Reference Guide. This document provides information about the 32-bit soft processor MicroBlaze, which is part of the Embedded Processor Development Kit (EDK). The document is intended as a guide to the MicroBlaze hardware architecture.

Manual Contents

This manual discusses the following topics speciﬁc to MicroBlaze soft processor:

•Core Architecture

•Bus Interfaces and Endianness

•Application Binary Interface

•Instruction Set Architecture

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this web-site. You can also directly access these resources using the provided URLs.

Resource	Description/URL

Tutorials	Tutorials covering Xilinx design ﬂows, from design entry to
	veriﬁcation and debugging
	http://support.xilinx.com/support/techsup/tutorials/index.htm

Answer Browser	Database of Xilinx solution records
	http://support.xilinx.com/xlnx/xil_ans_browser.jsp

Application Notes	Descriptions of device-speciﬁc design techniques and approaches
	http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?c
	ategory=Application+Notes

Data Book	Pages from The Programmable Logic Data Book, which contains
	device-speciﬁc information on Xilinx device characteristics,
	including readback, boundary scan, conﬁguration, length count,
	and debugging
	http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp

MicroBlaze Processor Reference Guide	www.xilinx.com	7
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 7

Xilinx EDK 8.2i manual Manual Contents, Additional Resources

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference GuideMicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual ContentsTypographical ConventionsConventions Meaning or Use Example Online DocumentUG081 v6.0 June 1 Overview FeaturesVersion Status Deprecated Active MicroBlaze ArchitectureInstructions Data Types and EndiannessFSR MSRESR EAROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PCPVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name DescriptionFSL EIPDCE ICEException Address Register EAR Buslock EnableESS Exception Status Register ESRSource/Destination Register Branch Target Register BTRProcessor Version Register PVR Floating Point Status Register FSRCusediv CFGCusebarrel DIVCunalignedexception CdebugenabledOP0EXEC UnexecCcachebytesize IcllCicachelinelen IcbsRstmsr CresetmsrPipeline Architecture ArchMemory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakException Causes ResetHardware Exceptions Equivalent PseudocodeHardware Breaks BreaksLatency InterruptUser Vector Exception Software BreaksInstruction Cache Instruction CacheOverview General Instruction Cache FunctionalityMSR Bit Data CacheInstruction Cache Operation Instruction Cache Software SupportData Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Arithmetic FormatRounding OperationsComparison Hardware Acceleration using FSLFast Simplex Link FSL ExceptionsDebug Overview Debug and TraceTrace Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb IxclDmrnw Dopb MicroBlaze Signal Interface DescriptionMfsl Imrnw IopbDAS Dlmb IAS IlmbDxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm DxclsAddr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface DescriptionDataRead031 DataWrite031ReadStrobe WriteStrobeGeneric Write Operation LMB TransactionsGeneric Read Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write OperationRD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write OperationCacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write MDM Debug Interface DescriptionTrace Interface Description Debug Interface DescriptionMicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core ConﬁgurabilityValues Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne CunalignedexceptionCicacheusefsl FfffCdcacheusefsl Data Types ScopeMicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type BDescription AddRegisters Altered Addi RD, rA, rB Registers Altered LatencyLogial and with Immediate Andi RD, rA, IMM AndiLogical and not AndnAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM AndniBranch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Branch if Less Than Blt BltBlti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Brad Instructions Unconditional BranchBra BrdMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rBBreak Immediate Brki RD, IMM BrkiBsra Instructions Barrel Shift BsrlBsll Bslli BsiBarrel Shift Immediate Bsrli BsraiInteger Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul FmulEsrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB DivideFcmp Esrec FSRIO,DO Cget GetGet from fsl interface NgetInteger Divide Idiv IdivIdivu Immediate ImmIMM ImmLoad Byte Unsigned LbuLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM LbuiLhu RD, rA, rB LhuLoad Halfword Unsigned Immediate Lhui RD, rA, IMM LhuiLoad Word Load Word Immediate Lwi RD, rA, IMM LwiMfs RD, rS MfsRead MSR and clear bits in MSR Msrclr RD, Imm MsrclrMsrset RD, Imm MsrsetMove To Special Purpose Register Mts RS, rA MtsInstructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM MuliLogical or Logical or with Immediate Ori RD, rA, IMM OriPattern Compare Byte Find Pcmpbf PcmpbfPattern Compare Equal Pcmpeq PcmpeqPattern Compare Not Equal Pcmpne PcmpneCput PutPut to fsl interface NputRsubk RsubArithmetic Reverse Subtract Rsub RsubcRsubik RsubiArithmetic Reverse Subtract Immediate Rsubi RsubicReturn from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Return from Subroutine Rtsd RA, IMM RtsdNone Store Byte Immediate Sbi RD, rA, IMM SbiSext16 RD, rA Sext16Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM ShiSra RD, rA SraShift Right with Carry Src RD, rA SrcShift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register AlteredWrite to Data Cache WdcWic Logical Exclusive or Xor RD, rA, rB XorLogical Exclusive or with Immediate XoriXori RA, rD, IMM 148