Machine Status Register MSR, Pvr, Cpvr | Xilinx EDK 8.2i specification

R

Chapter 1: MicroBlaze Architecture

031

↑

PC

Figure 1-3: PC

Table 1-8:Program Counter (PC)

Bits	Name	Description	Reset Value

0:31	PC	Program Counter	0x00000000
		Address of executing instruction,
		i.e. “mfs r2 0” will store the address
		of the mfs instruction itself in R2

Machine Status Register (MSR)

0

↑

CC

The Machine Status Register contains control and status bits for the processor. It can be read with an MFS instruction. When reading the MSR, bit 29 is replicated in bit 0 as the carry copy. MSR can be written using either an MTS instruction or the dedicated MSRSET and MSRCLR instructions.

When writing to the MSR, some of the bits will takes effect immediately (e.g Carry) and the remaining bits take effect one clock cycle later. Any value written to bit 0 is discarded. When used with an MTS or MFS instruction the MSR is speciﬁed by setting Sx = 0x0001.

21

22

23

24

25

26

27

28

29

30

31

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RESERVED

PVR EIP EE DCE DZ ICE FSL BIP

C

IE

BE

Figure 1-4: MSR

Table 1-9:Machine Status Register (MSR)

Bits

Name

Description

Reset Value

0

CC

Arithmetic Carry Copy

0

Copy of the Arithmetic Carry (bit 29).

CC is always the same as bit C.

1:20

Reserved

21

PVR

Processor Version Register exists

Based on

0 No Processor Version Register

option

C_PVR

1 Processor Version Register exists

Read only

22	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Image 22

Xilinx EDK 8.2i manual Machine Status Register MSR, 8Program Counter PC Bits Name Description Reset Value, Pvr, Cpvr

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions EAR MSRESR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers 9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVR ICE EIPDCE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR DIV CFGCusebarrel Cusediv Unexec CdebugenabledOP0EXEC Cunalignedexception Icbs IcllCicachelinelen Ccachebytesize Arch CresetmsrPipeline Architecture Rstmsr Memory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Equivalent Pseudocode ResetHardware Exceptions Exception Causes Breaks Hardware Breaks Software Breaks InterruptUser Vector Exception Latency General Instruction Cache Functionality Instruction CacheOverview Instruction Cache Instruction Cache Software Support Data CacheInstruction Cache Operation MSR Bit Data Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Operations FormatRounding Arithmetic Exceptions Hardware Acceleration using FSLFast Simplex Link FSL Comparison Debug Overview Debug and TraceTrace Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb IAS Ilmb Imrnw IopbDAS Dlmb Mfsl Dxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxclm Local Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031 WriteStrobe DataWrite031ReadStrobe DataRead031 Generic Write Operation LMB TransactionsGeneric Read Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2 RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write Debug Interface Description Debug Interface DescriptionTrace Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr Cnumberofrdaddrbrk Cicacheusefsl FfffCdcacheusefsl Scope Data Types MicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Type B FormatsType a Opcode Destination Reg Source Reg a Immediate Value Description AddRegisters Altered Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Logical and not AndnAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMM Branch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Blt Branch if Less Than Blt Blti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Brd Instructions Unconditional BranchBra Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Bsra Instructions Barrel Shift BsrlBsll Bsrai BsiBarrel Shift Immediate Bsrli Bslli Integer Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication Fmul Fdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Nget GetGet from fsl interface Cget Integer Divide Idiv IdivIdivu Imm Immediate ImmIMM Load Byte Unsigned LbuLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Nput PutPut to fsl interface Cput Rsubc RsubArithmetic Reverse Subtract Rsub Rsubk Rsubic RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubik Return from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Shift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Logical Exclusive or with Immediate XoriXori RA, rD, IMM 148