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Xilinx EDK 8.2i manual Format, Rounding, Operations, Arithmetic, Floating Point Unit FPU

Models: EDK 8.2i

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Floating Point Unit (FPU)

R

Format

An IEEE 754 single precision ﬂoating point number is composed of the following three ﬁelds:

1.1-bit sign

2.8-bit biased exponent

3.23-bit fraction (a.k.a. mantissa or signiﬁcand)

The ﬁelds are stored in a 32 bit word as deﬁned in Figure 1-11:

0

↑

1

↑

9

31

↑

sign

exponent

fraction

Figure 1-11:IEEE 754 Single Precision format

The value of a ﬂoating point number v in MicroBlaze has the following interpretation:

1.If exponent = 255 and fraction <> 0, then v= NaN, regardless of the sign bit

2.If exponent = 255 and fraction = 0, then v= (-1)sign* ∞

3.If 0 < exponent < 255, then v = (-1)sign* 2(exponent-127)* (1.fraction)

4.If exponent = 0 and fraction <> 0, then v = (-1)sign* 2-126* (0.fraction)

5.If exponent = 0 and fraction = 0, then v = (-1)sign* 0

For practical purposes only 3 and 5 are really useful, while the others all represent either an error or numbers that can no longer be represented with full precision in a 32 bit format.

Rounding

The MicroBlaze FPU only implements the default rounding mode, “Round-to-nearest”, speciﬁed in IEEE 754. By deﬁnition, the result of any ﬂoating point operation should return the nearest single precision value to the inﬁnitely precise result. If the two nearest representable values are equally near, then the one with its least signiﬁcant bit zero is returned.

Operations

All MicroBlaze FPU operations use the processors general purpose registers rather than a dedicated ﬂoating point register ﬁle, see “General Purpose Registers”.

Arithmetic

The FPU implements the following ﬂoating point operations:

•addition, fadd

•subtraction, fsub

•multiplication, fmul

•division, fdiv

MicroBlaze Processor Reference Guide	www.xilinx.com	41
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 41

Xilinx EDK 8.2i manual Format, Rounding, Operations, Arithmetic, Floating Point Unit FPU

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference GuideMicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual ContentsTypographical ConventionsConventions Meaning or Use Example Online DocumentUG081 v6.0 June 1 Overview FeaturesVersion Status Deprecated Active MicroBlaze ArchitectureInstructions Data Types and EndiannessESR MSREAR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Special Purpose Registers General Purpose RegistersProgram Counter PC RegistersMachine Status Register MSR 8Program Counter PC Bits Name Description Reset Value9Machine Status Register MSR Bits Name Description PVRDCE EIPICE FSLException Address Register EAR Buslock EnableESS Exception Status Register ESRSource/Destination Register Branch Target Register BTRProcessor Version Register PVR Floating Point Status Register FSRCusebarrel CFGDIV CusedivOP0EXEC CdebugenabledUnexec CunalignedexceptionCicachelinelen IcllIcbs CcachebytesizePipeline Architecture CresetmsrArch RstmsrBranches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakHardware Exceptions ResetEquivalent Pseudocode Exception CausesHardware Breaks BreaksUser Vector Exception InterruptSoftware Breaks LatencyOverview Instruction CacheGeneral Instruction Cache Functionality Instruction CacheInstruction Cache Operation Data CacheInstruction Cache Software Support MSR BitData Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Rounding FormatOperations ArithmeticFast Simplex Link FSL Hardware Acceleration using FSLExceptions ComparisonTrace Overview Debug and TraceDebug Overview MicroBlaze Architecture Ilmb MicroBlaze I/O OverviewIxcl DxclDmrnw Dopb MicroBlaze Signal Interface DescriptionDAS Dlmb Imrnw IopbIAS Ilmb MfslIxclm On-Chip Peripheral Bus OPB Interface DescriptionDxcls DxclmByteEnable03 LMB Signal InterfaceLocal Memory Bus LMB Interface Description Addr031ReadStrobe DataWrite031WriteStrobe DataRead031Generic Read Operation LMB TransactionsGeneric Write Operation Single Cycle Back-to-Back Read Operation Back-to-Back Write OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL Transactions Xilinx CacheLink XCL Interface DescriptionFSL BUS Write Operation FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Trace Interface Description Debug Interface DescriptionDebug Interface Description MDMMicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core ConﬁgurabilityValues Assigned Type Cusemsrinstr CusepcmpinstrPcmpne Cunalignedexception CnumberofrdaddrbrkCdcacheusefsl FfffCicacheusefsl Data Types Scope2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Type a FormatsType B Opcode Destination Reg Source Reg a Immediate ValueRegisters Altered AddDescription Addi RD, rA, rB Registers Altered LatencyLogial and with Immediate Andi RD, rA, IMM AndiAndn RD, rA, rB AndnLogical and not Logical and not with Immediate Andni RD, rA, IMM AndniBeqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Branch if Less Than Blt BltBltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Bra Instructions Unconditional BranchBrd BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rBBreak Immediate Brki RD, IMM BrkiBsll Instructions Barrel Shift BsrlBsra Barrel Shift Immediate Bsrli BsiBsrai BslliCmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Floating Point Arithmetic Multiplication Fmul FmulFloating Point Arithmetic Division FdivFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Get from fsl interface GetNget CgetIdivu IdivInteger Divide Idiv Immediate ImmIMM ImmLbu RD, rA, rB LbuLoad Byte Unsigned Load Byte Unsigned Immediate Lbui RD, rA, IMM LbuiLhu RD, rA, rB LhuLoad Halfword Unsigned Immediate Lhui RD, rA, IMM LhuiLoad Word Load Word Immediate Lwi RD, rA, IMM LwiMfs RD, rS MfsRead MSR and clear bits in MSR Msrclr RD, Imm MsrclrMsrset RD, Imm MsrsetMove To Special Purpose Register Mts RS, rA MtsInstructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM MuliLogical or Logical or with Immediate Ori RD, rA, IMM OriPattern Compare Byte Find Pcmpbf PcmpbfPattern Compare Equal Pcmpeq PcmpeqPattern Compare Not Equal Pcmpne PcmpnePut to fsl interface PutNput CputArithmetic Reverse Subtract Rsub RsubRsubc RsubkArithmetic Reverse Subtract Immediate Rsubi RsubiRsubic RsubikRtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Return from Subroutine Rtsd RA, IMM RtsdNone Store Byte Immediate Sbi RD, rA, IMM SbiSext16 RD, rA Sext16Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM ShiSra RD, rA SraShift Right with Carry Src RD, rA SrcSrl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register AlteredWrite to Data Cache WdcWic Logical Exclusive or Xor RD, rA, rB XorXori RA, rD, IMM XoriLogical Exclusive or with Immediate 148