Xilinx EDK 8.2i manual Data Cache, Instruction Cache Operation, Instruction Cache Software Support

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Chapter 1: MicroBlaze Architecture

For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00300000, C_ICACHE_HIGHADDR=0x0030ffff, C_CACHE_BYTE_SIZE=4096, and C_ICACHE_LINELEN=8; the cacheable memory of 64 kB uses 16 bits of byte address, and the 4 kB cache uses 12 bits of byte address, thus the required address tag width is: 16-12=4 bits. The total number of block RAM primitives required in this configuration is: 2 RAMB16 for storing the 1024 instruction words, and 1 RAMB16 for 128 cache line entries, each consisting of: 4 bits of tag, 8 word-valid bits, 1 line-valid bit. In total 3 RAMB16 primitives.

Instruction Cache Operation

For every instruction fetched, the instruction cache detects if the instruction address belongs to the cacheable segment. If the address is non-cacheable, the cache controller ignores the instruction and lets the OPB or LMB complete the request. If the address is cacheable, a lookup is performed on the tag memory to check if the requested address is currently cached. The lookup is successful if: the word and line valid bits are set, and the tag address matches the instruction address tag segment. On a cache miss, the cache controller will request the new instruction over the instruction CacheLink (IXCL) interface, and wait for the memory controller to return the associated cache line.

Instruction Cache Software Support

MSR Bit

The ICE bit in the MSR provides software control to enable and disable caches.

The contents of the cache are preserved by default when the cache is disabled. The user can invalidate cache lines using the WIC instruction or using the hardware debug logic of MicroBlaze.

WIC Instruction

The optional WIC instruction (C_ALLOW_ICACHE_WR=1) is used to invalidate cache lines in the instruction cache from an application. For a detailed description, please refer to Chapter 4, “MicroBlaze Instruction Set Architecture”. The cache must be disabled (MSR[ICE]=0) when the instruction is executed.

Data Cache

Overview

MicroBlaze may be used with an optional data cache for improved performance. The cached memory range must not include addresses in the LMB address range.

The data cache has the following features

•Direct mapped (1-way associative)

•Write-through

•User selectable cacheable memory address range

•Configurable cache size and tag size

•Caching over CacheLink (XCL) interface

•Option to use 4 or 8 word cache-lines

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	1-800-255-7778	UG081 (v6.0) June 1, 2006