Xilinx EDK 8.2i manual MicroBlaze Processor Reference Guide

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Chapter 2: MicroBlaze Signal Interface Description

Table 2-10:MicroBlaze Trace signals

Signal Name	Description	VHDL Type	Direction
Trace_Reg_Write1	Instruction writes to the	std_logic	output
	register file
Trace_Reg_Addr1	Destination register	std_logic_vector	output
	address	(0 to 4)
Trace_MSR_Reg1	Machine status register	std_logic_vector	output
		(0 to10)
Trace_New_Reg_Value1	Destination register	std_logic_vector	output
	update value	(0 to 31)
Trace_Exception_Taken1	Instruction result in taken	std_logic	output
	exception.
Trace_Exception_Kind1	Exception type. The	std_logic_vector	output
	description for the	(0 to 3)
	exception type is
	documented in Table 2-11
Trace_Jump_Taken1	Branch instruction	std_logic	output
	evaluated true i.e taken
Trace_Delay_Slot1	Instruction is in delay slot	std_logic	output
Trace_Data_Access1	Valid D-side memory	std_logic	output
	access
Trace_Data_Address1	Address for D-side	std_logic_vector	output
	memory access	(0 to 31)
Trace_Data_Write_Value1	Value for D-side memory	std_logic_vector	output
	write access	(0 to 31)
Trace_Data_Byte_Enable1	Byte enables for D-side	std_logic_vector	output
	memory access	(0 to 3)
Trace_Data_Read1	D-side memory access is a	std_logic	output
	read
Trace_Data_Write1	D-side memory access is a	std_logic	output
	write
Trace_DCache_Req	Data memory address is	std_logic	output
	within D-Cache range
Trace_DCache_Hit	Data memory address is	std_logic	output
	present in D-Cache
Trace_ICache_Req	Instruction memory	std_logic	output
	address is in I-Cache
	range
Trace_ICache_Hit	Instruction memory	std_logic	output
	address is present in I-
	Cache

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