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Xilinx EDK 8.2i manual MicroBlaze Instruction Set Architecture

Models: EDK 8.2i

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Chapter 4: MicroBlaze Instruction Set Architecture

Notes

The instructions brli and brali are not available.

By default, Type B Instructions will take the 16-bit IMM ﬁeld value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the imm instruction for details on using 32-bit immediate values.

A delay slot must not be used by the following: IMM, branch, or break instructions. This also applies to instructions causing recoverable exceptions (e.g. unalignement), when hardware exceptions are enabled. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.

94	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

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Xilinx EDK 8.2i manual MicroBlaze Instruction Set Architecture

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version RevisionUG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional ResourcesConventions TypographicalOnline Document Conventions Meaning or Use ExampleUG081 v6.0 June 1 Features OverviewMicroBlaze Architecture Version Status Deprecated ActiveData Types and Endianness InstructionsEAR MSRESR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVRICE EIPDCE FSLBuslock Enable Exception Address Register EARException Status Register ESR ESSBranch Target Register BTR Source/Destination RegisterFloating Point Status Register FSR Processor Version Register PVRDIV CFGCusebarrel CusedivUnexec CdebugenabledOP0EXEC CunalignedexceptionIcbs IcllCicachelinelen CcachebytesizeArch CresetmsrPipeline Architecture RstmsrMemory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakEquivalent Pseudocode ResetHardware Exceptions Exception CausesBreaks Hardware BreaksSoftware Breaks InterruptUser Vector Exception LatencyGeneral Instruction Cache Functionality Instruction CacheOverview Instruction CacheInstruction Cache Software Support Data CacheInstruction Cache Operation MSR BitData Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Operations FormatRounding ArithmeticExceptions Hardware Acceleration using FSLFast Simplex Link FSL ComparisonDebug Overview Debug and TraceTrace Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb DxclMicroBlaze Signal Interface Description Dmrnw DopbIAS Ilmb Imrnw IopbDAS Dlmb MfslDxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm DxclmLocal Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031WriteStrobe DataWrite031ReadStrobe DataRead031Generic Write Operation LMB TransactionsGeneric Read Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write Debug Interface Description Debug Interface DescriptionTrace Interface Description MDMMicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind DescriptionValues Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr CnumberofrdaddrbrkCicacheusefsl FfffCdcacheusefsl Scope Data TypesMicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Type B FormatsType a Opcode Destination Reg Source Reg a Immediate ValueDescription AddRegisters Altered Addi Registers Altered Latency RD, rA, rBAndi Logial and with Immediate Andi RD, rA, IMMLogical and not AndnAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMMBranch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Blt Branch if Less Than BltBlti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Brd Instructions Unconditional BranchBra BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB MsrbipBrki Break Immediate Brki RD, IMMBsra Instructions Barrel Shift BsrlBsll Bsrai BsiBarrel Shift Immediate Bsrli BslliInteger Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication FmulFdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Nget GetGet from fsl interface CgetInteger Divide Idiv IdivIdivu Imm Immediate ImmIMMLoad Byte Unsigned LbuLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMMLhu Lhu RD, rA, rBLhui Load Halfword Unsigned Immediate Lhui RD, rA, IMMLoad Word Lwi Load Word Immediate Lwi RD, rA, IMMMfs Mfs RD, rSMsrclr Read MSR and clear bits in MSR Msrclr RD, ImmMsrset Msrset RD, ImmMts Move To Special Purpose Register Mts RS, rAInstructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMMLogical or Ori Logical or with Immediate Ori RD, rA, IMMPcmpbf Pattern Compare Byte Find PcmpbfPcmpeq Pattern Compare Equal PcmpeqPcmpne Pattern Compare Not Equal PcmpneNput PutPut to fsl interface CputRsubc RsubArithmetic Reverse Subtract Rsub RsubkRsubic RsubiArithmetic Reverse Subtract Immediate Rsubi RsubikReturn from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMMNone Sbi Store Byte Immediate Sbi RD, rA, IMMSext16 Sext16 RD, rASign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMMSra Sra RD, rASrc Shift Right with Carry Src RD, rAShift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMMWdc Write to Data CacheWic Xor Logical Exclusive or Xor RD, rA, rBLogical Exclusive or with Immediate XoriXori RA, rD, IMM 148