Xilinx EDK 8.2i manual Instruction Cache Read Miss, Data Cache Read Miss, Data Cache Write

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Chapter 2: MicroBlaze Signal Interface Description

The CacheLink solution uses one incoming (slave) and one outgoing (master) FSL per cache controller. The outgoing FSL is used to send access requests, while the incoming FSL is used for receiving the requested cache lines. CacheLink also uses a specific encoding of the transaction information over the FSL data and control signals.

The cache lines used for reads in the CacheLink protocol are 4 words long. Each cache line is expected to start with the critical word first. I.e. if an access to address 0x348 is a miss, then the returned cache line should have the following address sequence: 0x348, 0x34c, 0x340, 0x344. The cache controller will forward the first word to the execution unit as well as store it in the cache memory. This allows execution to resume as soon as the first word is back. The cache controller then follows through by filling up the cache line with the remaining 3 words as they are received.

All write operations to the data cache are single-word write-through.

Instruction Cache Read Miss

On a read miss the cache controller will perform the following sequence:

1.Write the word aligned(1) missed address to ICACHE_FSL_OUT_Data, with the control bit set low (ICACHE_FSL_OUT_Control = 0) to indicate a read access

2.Wait until ICACHE_FSL_IN_Exists goes high to indicate that data is available

3.Store the word from ICACHE_FSL_IN_Data to the cache

4.Forward the critical word to the execution unit in order to resume execution

5.Repeat 3 and 4 for the subsequent 3 words in the cache line

Data Cache Read Miss

On a read miss the cache controller will perform the following sequence:

1.If DCACHE_FSL_OUT_Full = 1 then stall until it goes low

2.Write the word aligned1 missed address to DCACHE_FSL_OUT_Data, with the control bit set low (DCACHE_FSL_OUT_Control = 0) to indicate a read access

3.Wait until DCACHE_FSL_IN_Exists goes high to indicate that data is available

4.Store the word from DCACHE_FSL_IN_Data to the cache

5.Forward the critical word to the execution unit in order to resume execution

6.Repeat 3 and 4 for the subsequent 3 words in the cache line

Data Cache Write

Note that writes to the data cache always are write-through, and thus there will be a write over the CacheLink regardless of whether there was a hit or miss in the cache. On a write the cache controller will perform the following sequence:

1.If DCACHE_FSL_OUT_Full = 1 then stall until it goes low

2.Write the missed address to DCACHE_FSL_OUT_Data, with the control bit set high (DCACHE_FSL_OUT_Control = 1) to indicate a write access. The two least-significant bits (30:31) of the address are used to encode byte and half-word enables: 0b00=byte0,

1.Byte and halfword read misses are naturally expected to return complete words, the cache controller then provides the execution unit with the correct bytes.

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	1-800-255-7778	UG081 (v6.0) June 1, 2006