UG081 v6.0 June 1
MicroBlaze Processor Reference Guide
 MicroBlaze Processor Reference Guide
 Date Version Revision
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
 UG081 v6.0 June 1
 Preface About This Guide
 MicroBlaze Application Binary Interface
 Additional Resources
Manual Contents
 Typographical
Conventions
 Conventions Meaning or Use Example
Online Document
 UG081 v6.0 June 1
 Overview
Features
 Version Status Deprecated Active
MicroBlaze Architecture
 Instructions
Data Types and Endianness
 ESR
MSR
EAR
FSR
 Op1 if cond else op2
 MicroBlaze Processor Reference Guide
 MicroBlaze Processor Reference Guide UG081 v6.0 June 1
 MicroBlaze Processor Reference Guide
 MicroBlaze Processor Reference Guide UG081 v6.0 June 1
 Registers
 Special Purpose Registers
General Purpose Registers
Program Counter PC
Registers
 Machine Status Register MSR
8Program Counter PC Bits Name Description Reset Value
9Machine Status Register MSR Bits Name Description
PVR
 DCE
EIP
ICE
FSL
 Exception Address Register EAR
Buslock Enable
 ESS
Exception Status Register ESR
 Source/Destination Register
Branch Target Register BTR
 Processor Version Register PVR
Floating Point Status Register FSR
 Cusebarrel
CFG
DIV
Cusediv
 OP0EXEC
Cdebugenabled
Unexec
Cunalignedexception
 Cicachelinelen
Icll
Icbs
Ccachebytesize
 Pipeline Architecture
Cresetmsr
Arch
Rstmsr
 Delay Slots
Memory Architecture
Branches
 Reset, Interrupts, Exceptions, and Break
Reset, Interrupts, Exceptions, and Break
 Hardware Exceptions
Reset
Equivalent Pseudocode
Exception Causes
 Hardware Breaks
Breaks
 User Vector Exception
Interrupt
Software Breaks
Latency
 Overview
Instruction Cache
General Instruction Cache Functionality
Instruction Cache
 Instruction Cache Operation
Data Cache
Instruction Cache Software Support
MSR Bit
 General Data Cache Functionality
Data Cache Operation
Data Cache
 Floating Point Unit FPU
Data Cache Software Support
WDC Instruction
 Rounding
Format
Operations
Arithmetic
 Fast Simplex Link FSL
Hardware Acceleration using FSL
Exceptions
Comparison
 Debug and Trace
Debug Overview
Trace Overview
 MicroBlaze Architecture
 Ilmb
MicroBlaze I/O Overview
Ixcl
Dxcl
 Dmrnw Dopb
MicroBlaze Signal Interface Description
 DAS Dlmb
Imrnw Iopb
IAS Ilmb
Mfsl
 Ixclm
On-Chip Peripheral Bus OPB Interface Description
Dxcls
Dxclm
 ByteEnable03
LMB Signal Interface
Local Memory Bus LMB Interface Description
Addr031
 ReadStrobe
DataWrite031
WriteStrobe
DataRead031
 LMB Transactions
Generic Write Operation
Generic Read Operation
 Single Cycle Back-to-Back Read Operation
Back-to-Back Write Operation
Back-to-Back Mixed Read/Write Operation
BE0 BE1 BE2
 Read and Write Data Steering
RD1623 RD2431
RD07 RD815 RD1623 RD2431
 Master FSL Signal Interface
Slave FSL Signal Interface
Fast Simplex Link FSL Interface Description
 FSL Transactions
Xilinx CacheLink XCL Interface Description
FSL BUS Write Operation
FSL BUS Read Operation
 CacheLink Signal Interface
 CacheLink Transactions
 Instruction Cache Read Miss
Data Cache Read Miss
Data Cache Write
 Trace Interface Description
Debug Interface Description
Debug Interface Description
MDM
 MicroBlaze Processor Reference Guide
 11 Type of Trace Exception TraceExceptionKind Description
MicroBlaze Core Configurability
 Values Assigned Type
 Cusemsrinstr
Cusepcmpinstr
Pcmpne Cunalignedexception
Cnumberofrdaddrbrk
 Ffff
Cicacheusefsl
Cdcacheusefsl
 Data Types
Scope
 Register Usage Conventions
MicroBlaze Application Binary Interface
2Register usage conventions Type Enforcement Purpose
 Stack Convention
Stack Convention
 High Memory Low Memory Func
 Memory Model
 Interrupt and Exception Handling
 1Symbol notation Meaning
Summary
Notation
 Type a
Formats
Type B
Opcode Destination Reg Source Reg a Immediate Value
 Add
Description
Registers Altered
 Addi
 RD, rA, rB
Registers Altered Latency
 Logial and with Immediate Andi RD, rA, IMM
Andi
 Andn
Logical and not
Andn RD, rA, rB
 Logical and not with Immediate Andni RD, rA, IMM
Andni
 Beq
Branch if Equal Beq
Beqd
 Beqi
Branch Immediate if Equal Beqi
Beqid
 Bge
Branch if Greater or Equal Bge
Bged
 Bgei
Branch Immediate if Greater or Equal Bgei
Bgeid
 Bgt
Branch if Greater Than Bgt
Bgtd
 Bgti
Branch Immediate if Greater Than Bgti
Bgtid
 Ble
Branch if Less or Equal Ble
Bled
 Blei
Branch Immediate if Less or Equal Blei
Bleid
 Branch if Less Than Blt
Blt
 Blti
Blti
Bltid
 Bne
Branch if Not Equal Bne
Bned
 Bnei
Branch Immediate if Not Equal Bnei
Bneid
 Bra
Instructions Unconditional Branch
Brd
Brad
 MicroBlaze Instruction Set Architecture
 Bri
 MicroBlaze Instruction Set Architecture
 Msrbip
Instructions BrkBreak RD, rB
 Break Immediate Brki RD, IMM
Brki
 Instructions Barrel Shift Bsrl
Bsra
Bsll
 Barrel Shift Immediate Bsrli
Bsi
Bsrai
Bslli
 Cmp
Integer Compare Cmp
Cmpu
 Fadd
Floating Point Arithmetic Add Fadd
Esrec FSRIO,UF,OF,DO
 Frsub
Reverse Floating Point Arithmetic Subtraction
Frsub RD, rA, rB Reverse subtract
 Floating Point Arithmetic Multiplication Fmul
Fmul
 Floating Point Arithmetic Division
Fdiv
Fdiv RD, rA, rB Divide
Esrec FSRIO,UF,OF,DO,DZ
 Fcmp
 Esrec FSRIO,DO
 Get from fsl interface
Get
Nget
Cget
 Idiv
Integer Divide Idiv
Idivu
 Immediate ImmIMM
Imm
 Lbu
Load Byte Unsigned
Lbu RD, rA, rB
 Load Byte Unsigned Immediate Lbui RD, rA, IMM
Lbui
 Lhu RD, rA, rB
Lhu
 Load Halfword Unsigned Immediate Lhui RD, rA, IMM
Lhui
 Load Word
 Load Word Immediate Lwi RD, rA, IMM
Lwi
 Mfs RD, rS
Mfs
 Read MSR and clear bits in MSR Msrclr RD, Imm
Msrclr
 Msrset RD, Imm
Msrset
 Move To Special Purpose Register Mts RS, rA
Mts
 Instructions Mul Multiply RD, rA, rB
 Multiply Immediate Muli RD, rA, IMM
Muli
 Logical or
 Logical or with Immediate Ori RD, rA, IMM
Ori
 Pattern Compare Byte Find Pcmpbf
Pcmpbf
 Pattern Compare Equal Pcmpeq
Pcmpeq
 Pattern Compare Not Equal Pcmpne
Pcmpne
 Put to fsl interface
Put
Nput
Cput
 Arithmetic Reverse Subtract Rsub
Rsub
Rsubc
Rsubk
 Arithmetic Reverse Subtract Immediate Rsubi
Rsubi
Rsubic
Rsubik
 Rtbd
Return from Break
Rtbd RA, IMM
 Rtid
Return from Interrupt Rtid RA, IMM
Msrie
 Rted
Return from Exception Rted RA, IMM
Msree Msreip ESR
 Return from Subroutine Rtsd RA, IMM
Rtsd
 None
 Store Byte Immediate Sbi RD, rA, IMM
Sbi
 Sext16 RD, rA
Sext16
 Sext8
Sign Extend Byte
Sext8 RD, rA
 Instructions Store Halfword RD, rA, rB
 Store Halfword Immediate Shi RD, rA, IMM
Shi
 Sra RD, rA
Sra
 Shift Right with Carry Src RD, rA
Src
 Srl
Shift Right Logical
Srl RD, rA
 Addr ← rA + rB Addr3031 ← MemAddr ← rD031
 Store Word Immediate Swi RD, rA, IMM
Register Altered
 Write to Data Cache
Wdc
 Wic
 Logical Exclusive or Xor RD, rA, rB
Xor
 Xori
Logical Exclusive or with Immediate
Xori RA, rD, IMM
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