Xilinx EDK 8.2i manual Pipeline Architecture, Rstmsr, Cresetmsr, Mem

Pipeline Architecture

Table 1-25:Processor Version Register 10 (PVR10)

R

	Bits	Name		Description	Value
	0:7	ARCH	Target architecture:		Defined by option C_TARGET
			0x4	= Virtex2
			0x5	= Virtex2Pro
			0x6	= Spartan3
			0x7	= Virtex4
			0x8	= Virtex5
			0x9	= Spartan3E
	8:31	Reserved			0
Table 1-26:Processor Version Register 11 (PVR11)
	Bits	Name		Description	Value
	0:20	DO	Reset value for MSR		0
	21:31	RSTMSR	Reset value for MSR		C_RESET_MSR

Pipeline Architecture

MicroBlaze instruction execution is pipelined. The pipeline is divided into five stages:

Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and Writeback (WB).

For most instructions, each stage takes one clock cycle to complete. Consequently, it takes five clock cycles for a specific instruction to complete, and one instruction is completed on every cycle. A few instructions require multiple clock cycles in the execute stage to complete. This is achieved by stalling the pipeline.

instruction 1

instruction 2

instruction 3

cycle	cycle	cycle	cycle	cycle	cycle	cycle	cycle	cycle
1	2	3	4	5	6	7	8	9
IF	OF	EX	MEM	WB
	IF	OF	EX	MEM	MEM	MEM	WB
		IF	OF	EX	Stall	Stall	MEM	WB

When executing from slower memory, instruction fetches may take multiple cycles. This additional latency will directly affect the efficiency of the pipeline. MicroBlaze implements an instruction prefetch buffer that reduces the impact of such multi-cycle instruction memory latency. While the pipeline is stalled by a multi-cycle instruction in the execution stage the prefetch buffer continues to load sequential instructions. Once the pipeline resumes execution the fetch stage can load new instructions directly from the prefetch buffer rather than having to wait for the instruction memory access to complete.

MicroBlaze Processor Reference Guide	www.xilinx.com	31
UG081 (v6.0) June 1, 2006	1-800-255-7778