Lhui | Xilinx EDK 8.2i specification

R

Chapter 4: MicroBlaze Instruction Set Architecture

lhui

Load Halfword Unsigned Immediate

lhui	rD, rA, IMM

1 1 1 0 0 1

rD

rA

IMM

0

6

11

16

31

Description

Loads a halfword (16 bits) from the halfword aligned memory location that results from adding the contents of register rA and the value in IMM, sign-extended to 32 bits. The data is placed in the least signiﬁcant halfword of register rD and the most signiﬁcant halfword in rD is cleared.

Pseudocode

Addr ← (rA) + sext(IMM) Addr[31] ← 0 (rD)[16:31] ← Mem(Addr) (rD)[0:15] ← 0

Registers Altered

•rD, unless unaligned data access exception is generated, in which case the register is unchanged.

•ESR [W]

Latency

1 cycle

Note

By default, Type B Instructions will take the 16-bit IMM ﬁeld value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the imm instruction for details on using 32-bit immediate values.

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Image 112

Xilinx EDK 8.2i manual Load Halfword Unsigned Immediate Lhui RD, rA, IMM

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions MSR ESREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers General Purpose Registers Special Purpose RegistersProgram Counter PC Registers 8Program Counter PC Bits Name Description Reset Value Machine Status Register MSR9Machine Status Register MSR Bits Name Description PVR EIP DCEICE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR CFG CusebarrelDIV Cusediv Cdebugenabled OP0EXECUnexec Cunalignedexception Icll CicachelinelenIcbs Ccachebytesize Cresetmsr Pipeline ArchitectureArch Rstmsr Memory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Reset Hardware ExceptionsEquivalent Pseudocode Exception Causes Breaks Hardware Breaks Interrupt User Vector ExceptionSoftware Breaks Latency Instruction Cache OverviewGeneral Instruction Cache Functionality Instruction Cache Data Cache Instruction Cache OperationInstruction Cache Software Support MSR Bit Data Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Format RoundingOperations Arithmetic Hardware Acceleration using FSL Fast Simplex Link FSLExceptions Comparison Debug Overview Debug and TraceTrace Overview MicroBlaze Architecture MicroBlaze I/O Overview IlmbIxcl Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb Imrnw Iopb DAS DlmbIAS Ilmb Mfsl On-Chip Peripheral Bus OPB Interface Description IxclmDxcls Dxclm LMB Signal Interface ByteEnable03Local Memory Bus LMB Interface Description Addr031 DataWrite031 ReadStrobeWriteStrobe DataRead031 Generic Write Operation LMB TransactionsGeneric Read Operation Back-to-Back Write Operation Single Cycle Back-to-Back Read OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description Xilinx CacheLink XCL Interface Description FSL TransactionsFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write Debug Interface Description Trace Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Cusepcmpinstr CusemsrinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Cicacheusefsl FfffCdcacheusefsl Scope Data Types MicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Formats Type aType B Opcode Destination Reg Source Reg a Immediate Value Description AddRegisters Altered Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Logical and not AndnAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMM Branch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Blt Branch if Less Than Blt Blti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Instructions Unconditional Branch BraBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Bsra Instructions Barrel Shift BsrlBsll Bsi Barrel Shift Immediate BsrliBsrai Bslli Integer Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication Fmul Fdiv Floating Point Arithmetic DivisionFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get Get from fsl interfaceNget Cget Integer Divide Idiv IdivIdivu Imm Immediate ImmIMM Load Byte Unsigned LbuLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Put Put to fsl interfaceNput Cput Rsub Arithmetic Reverse Subtract RsubRsubc Rsubk Rsubi Arithmetic Reverse Subtract Immediate RsubiRsubic Rsubik Return from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Shift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Logical Exclusive or with Immediate XoriXori RA, rD, IMM 148