Xilinx EDK 8.2i Icll, Cicachelinelen, Icbs, Ccachebytesize, Dcts, Cdcacheaddrtag, Dcw, Dcll, Dcbs

R

Chapter 1: MicroBlaze Architecture

Table 1-19:Processor Version Register 4 (PVR4) (Continued)

			Bits	Name	Description	Value
	8:10			ICLL	Instruction cache line length	C_ICACHE_LINE_LEN
					2^n
	11:15			ICBS	Instruction cache byte size 2^n	C_CACHE_BYTE_SIZE
	16:31			Reserved		0
Table 1-20:Processor Version Register 5 (PVR5)
			Bits	Name	Description	Value
		0		DCU	Use data cache	C_USE_DCACHE
		1:5		DCTS	Data cache tag size	C_DCACHE_ADDR_TAG
		6		Reserved		1
		7		DCW	Allow data cache write	C_ALLOW_DCACHE_WR
		8:10		DCLL	Data cache line length 2^n	C_DCACHE_LINE_LEN
		11:15		DCBS	Data cache byte size 2^n	C_DCACHE_BYTE_SIZE
		16:31		Reserved		0
Table 1-21:Processor Version Register 6 (PVR6)
			Bits	Name	Description	Value
			0:31	ICBA	Instruction Cache Base Address	C_ICACHE_BASEADDR
Table 1-22:Processor Version Register 7 (PVR7)
			Bits	Name	Description	Value
			0:31	ICHA	Instruction Cache High	C_ICACHE_HIGHADDR
					Address
Table 1-23:Processor Version Register 8 (PVR8)
			Bits	Name	Description	Value
		0:31		DCBA	Data Cache Base Address	C_DCACHE_BASEADDR
Table 1-24:Processor Version Register 9 (PVR9)
			Bits	Name	Description	Value
	0:31			DCHA	Data Cache High Address	C_DCACHE_HIGHADDR

30	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006