Return from Subroutine Rtsd RA, IMM | Xilinx EDK 8.2i specification

R

Chapter 4: MicroBlaze Instruction Set Architecture

rtsd

Return from Subroutine

rtsd

rA, IMM

1 0 1 1 0 1

1 0 0 0 0

rA

IMM

0

6

11

16

31

Description

Return from subroutine will branch to the location speciﬁed by the contents of rA plus the IMM ﬁeld, sign-extended to 32 bits.

This instruction always has a delay slot. The instruction following the RTSD is always executed before the branch target.

Pseudocode

PC ← (rA) + sext(IMM)

allow following instruction to complete execution

Registers Altered

•PC

Latency

2 cycles

Note

Convention is to use general purpose register r15 as rA.

A delay slot must not be used by the following: IMM, branch, or break instructions. This also applies to instructions causing recoverable exceptions (e.g. unalignement), when hardware exceptions are enabled. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.

132	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Image 132

Xilinx EDK 8.2i manual Return from Subroutine Rtsd RA, IMM

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions MSR ESREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers General Purpose Registers Special Purpose RegistersProgram Counter PC Registers 8Program Counter PC Bits Name Description Reset Value Machine Status Register MSR9Machine Status Register MSR Bits Name Description PVR EIP DCEICE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR CFG CusebarrelDIV Cusediv Cdebugenabled OP0EXECUnexec Cunalignedexception Icll CicachelinelenIcbs Ccachebytesize Cresetmsr Pipeline ArchitectureArch Rstmsr Delay Slots Memory ArchitectureBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Reset Hardware ExceptionsEquivalent Pseudocode Exception Causes Breaks Hardware Breaks Interrupt User Vector ExceptionSoftware Breaks Latency Instruction Cache OverviewGeneral Instruction Cache Functionality Instruction Cache Data Cache Instruction Cache OperationInstruction Cache Software Support MSR Bit General Data Cache Functionality Data Cache OperationData Cache Floating Point Unit FPU Data Cache Software SupportWDC Instruction Format RoundingOperations Arithmetic Hardware Acceleration using FSL Fast Simplex Link FSLExceptions Comparison Debug and Trace Debug OverviewTrace Overview MicroBlaze Architecture MicroBlaze I/O Overview IlmbIxcl Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb Imrnw Iopb DAS DlmbIAS Ilmb Mfsl On-Chip Peripheral Bus OPB Interface Description IxclmDxcls Dxclm LMB Signal Interface ByteEnable03Local Memory Bus LMB Interface Description Addr031 DataWrite031 ReadStrobeWriteStrobe DataRead031 LMB Transactions Generic Write OperationGeneric Read Operation Back-to-Back Write Operation Single Cycle Back-to-Back Read OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 Read and Write Data Steering RD1623 RD2431RD07 RD815 RD1623 RD2431 Master FSL Signal Interface Slave FSL Signal InterfaceFast Simplex Link FSL Interface Description Xilinx CacheLink XCL Interface Description FSL TransactionsFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read MissData Cache Write Debug Interface Description Trace Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Cusepcmpinstr CusemsrinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Ffff CicacheusefslCdcacheusefsl Scope Data Types Register Usage Conventions MicroBlaze Application Binary Interface2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling 1Symbol notation Meaning SummaryNotation Formats Type aType B Opcode Destination Reg Source Reg a Immediate Value Add DescriptionRegisters Altered Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Andn Logical and notAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMM Beq Branch if Equal BeqBeqd Beqi Branch Immediate if Equal BeqiBeqid Bge Branch if Greater or Equal BgeBged Bgei Branch Immediate if Greater or Equal BgeiBgeid Bgt Branch if Greater Than BgtBgtd Bgti Branch Immediate if Greater Than BgtiBgtid Ble Branch if Less or Equal BleBled Blei Branch Immediate if Less or Equal BleiBleid Blt Branch if Less Than Blt Blti BltiBltid Bne Branch if Not Equal BneBned Bnei Branch Immediate if Not Equal BneiBneid Instructions Unconditional Branch BraBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Instructions Barrel Shift Bsrl BsraBsll Bsi Barrel Shift Immediate BsrliBsrai Bslli Cmp Integer Compare CmpCmpu Fadd Floating Point Arithmetic Add FaddEsrec FSRIO,UF,OF,DO Frsub Reverse Floating Point Arithmetic SubtractionFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication Fmul Fdiv Floating Point Arithmetic DivisionFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get Get from fsl interfaceNget Cget Idiv Integer Divide IdivIdivu Imm Immediate ImmIMM Lbu Load Byte UnsignedLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Put Put to fsl interfaceNput Cput Rsub Arithmetic Reverse Subtract RsubRsubc Rsubk Rsubi Arithmetic Reverse Subtract Immediate RsubiRsubic Rsubik Rtbd Return from BreakRtbd RA, IMM Rtid Return from Interrupt Rtid RA, IMMMsrie Rted Return from Exception Rted RA, IMMMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sext8 Sign Extend ByteSext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Srl Shift Right LogicalSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Xori Logical Exclusive or with ImmediateXori RA, rD, IMM 148