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Xilinx EDK 8.2i manual Logical or with Immediate Ori RD, rA, IMM

Models: EDK 8.2i

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Chapter 4: MicroBlaze Instruction Set Architecture

ori

Logical OR with Immediate

ori	rD, rA, IMM

1 0 1 0 0 0

IMM

Description

The contents of register rA are ORed with the extended IMM ﬁeld, sign-extended to 32 bits; the result is placed into register rD.

Pseudocode

(rD) ← (rA) ∨ (IMM)

Registers Altered

•rD

Latency

1 cycle

Note

By default, Type B Instructions will take the 16-bit IMM ﬁeld value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the imm instruction for details on using 32-bit immediate values.

122	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Page 122

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Xilinx EDK 8.2i manual Logical or with Immediate Ori RD, rA, IMM

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version RevisionUG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional ResourcesConventions TypographicalOnline Document Conventions Meaning or Use ExampleUG081 v6.0 June 1 Features OverviewMicroBlaze Architecture Version Status Deprecated ActiveData Types and Endianness InstructionsEAR MSRESR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVRICE EIPDCE FSLBuslock Enable Exception Address Register EARException Status Register ESR ESSBranch Target Register BTR Source/Destination RegisterFloating Point Status Register FSR Processor Version Register PVRDIV CFGCusebarrel CusedivUnexec CdebugenabledOP0EXEC CunalignedexceptionIcbs IcllCicachelinelen CcachebytesizeArch CresetmsrPipeline Architecture RstmsrBranches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakEquivalent Pseudocode ResetHardware Exceptions Exception CausesBreaks Hardware BreaksSoftware Breaks InterruptUser Vector Exception LatencyGeneral Instruction Cache Functionality Instruction CacheOverview Instruction CacheInstruction Cache Software Support Data CacheInstruction Cache Operation MSR BitData Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Operations FormatRounding ArithmeticExceptions Hardware Acceleration using FSLFast Simplex Link FSL ComparisonTrace Overview Debug and TraceDebug Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb DxclMicroBlaze Signal Interface Description Dmrnw DopbIAS Ilmb Imrnw IopbDAS Dlmb MfslDxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm DxclmLocal Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031WriteStrobe DataWrite031ReadStrobe DataRead031Generic Read Operation LMB TransactionsGeneric Write Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Debug Interface Description Debug Interface DescriptionTrace Interface Description MDMMicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind DescriptionValues Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr CnumberofrdaddrbrkCdcacheusefsl FfffCicacheusefsl Scope Data Types2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Type B FormatsType a Opcode Destination Reg Source Reg a Immediate ValueRegisters Altered AddDescription Addi Registers Altered Latency RD, rA, rBAndi Logial and with Immediate Andi RD, rA, IMMAndn RD, rA, rB AndnLogical and not Andni Logical and not with Immediate Andni RD, rA, IMMBeqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Blt Branch if Less Than BltBltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Brd Instructions Unconditional BranchBra BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB MsrbipBrki Break Immediate Brki RD, IMMBsll Instructions Barrel Shift BsrlBsra Bsrai BsiBarrel Shift Immediate Bsrli BslliCmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Fmul Floating Point Arithmetic Multiplication FmulFdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Nget GetGet from fsl interface CgetIdivu IdivInteger Divide Idiv Imm Immediate ImmIMMLbu RD, rA, rB LbuLoad Byte Unsigned Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMMLhu Lhu RD, rA, rBLhui Load Halfword Unsigned Immediate Lhui RD, rA, IMMLoad Word Lwi Load Word Immediate Lwi RD, rA, IMMMfs Mfs RD, rSMsrclr Read MSR and clear bits in MSR Msrclr RD, ImmMsrset Msrset RD, ImmMts Move To Special Purpose Register Mts RS, rAInstructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMMLogical or Ori Logical or with Immediate Ori RD, rA, IMMPcmpbf Pattern Compare Byte Find PcmpbfPcmpeq Pattern Compare Equal PcmpeqPcmpne Pattern Compare Not Equal PcmpneNput PutPut to fsl interface CputRsubc RsubArithmetic Reverse Subtract Rsub RsubkRsubic RsubiArithmetic Reverse Subtract Immediate Rsubi RsubikRtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Rtsd Return from Subroutine Rtsd RA, IMMNone Sbi Store Byte Immediate Sbi RD, rA, IMMSext16 Sext16 RD, rASext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMMSra Sra RD, rASrc Shift Right with Carry Src RD, rASrl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMMWdc Write to Data CacheWic Xor Logical Exclusive or Xor RD, rA, rBXori RA, rD, IMM XoriLogical Exclusive or with Immediate 148