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Xilinx EDK 8.2i manual Load Word Immediate Lwi RD, rA, IMM

Models: EDK 8.2i

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Chapter 4: MicroBlaze Instruction Set Architecture

lwi

Load Word Immediate

lwi	rD, rA, IMM

1 1 1 0 1 0

IMM

Description

Loads a word (32 bits) from the word aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits. The data is placed in register rD.

Pseudocode

Addr ← (rA) + sext(IMM) Addr[30:31] ← 00

(rD) ← Mem(Addr)

Registers Altered

•rD, unless unaligned data access exception is generated, in which case the register is unchanged.

•ESR [W]

Latency

1 cycle

Note

By default, Type B Instructions will take the 16-bit IMM ﬁeld value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the imm instruction for details on using 32-bit immediate values.

114	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Page 114

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Xilinx EDK 8.2i manual Load Word Immediate Lwi RD, rA, IMM

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version RevisionUG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional ResourcesConventions TypographicalOnline Document Conventions Meaning or Use ExampleUG081 v6.0 June 1 Features OverviewMicroBlaze Architecture Version Status Deprecated ActiveData Types and Endianness InstructionsEAR MSRESR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVRICE EIPDCE FSLBuslock Enable Exception Address Register EARException Status Register ESR ESSBranch Target Register BTR Source/Destination RegisterFloating Point Status Register FSR Processor Version Register PVRDIV CFGCusebarrel CusedivUnexec CdebugenabledOP0EXEC CunalignedexceptionIcbs IcllCicachelinelen CcachebytesizeArch CresetmsrPipeline Architecture RstmsrDelay Slots Memory ArchitectureBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakEquivalent Pseudocode ResetHardware Exceptions Exception CausesBreaks Hardware BreaksSoftware Breaks InterruptUser Vector Exception LatencyGeneral Instruction Cache Functionality Instruction CacheOverview Instruction CacheInstruction Cache Software Support Data CacheInstruction Cache Operation MSR BitGeneral Data Cache Functionality Data Cache OperationData Cache Floating Point Unit FPU Data Cache Software SupportWDC Instruction Operations FormatRounding ArithmeticExceptions Hardware Acceleration using FSLFast Simplex Link FSL ComparisonDebug and Trace Debug OverviewTrace Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb DxclMicroBlaze Signal Interface Description Dmrnw DopbIAS Ilmb Imrnw IopbDAS Dlmb MfslDxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm DxclmLocal Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031WriteStrobe DataWrite031ReadStrobe DataRead031LMB Transactions Generic Write OperationGeneric Read Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2Read and Write Data Steering RD1623 RD2431RD07 RD815 RD1623 RD2431 Master FSL Signal Interface Slave FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read MissData Cache Write Debug Interface Description Debug Interface DescriptionTrace Interface Description MDMMicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind DescriptionValues Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr CnumberofrdaddrbrkFfff CicacheusefslCdcacheusefsl Scope Data TypesRegister Usage Conventions MicroBlaze Application Binary Interface2Register usage conventions Type Enforcement Purpose Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling 1Symbol notation Meaning SummaryNotation Type B FormatsType a Opcode Destination Reg Source Reg a Immediate ValueAdd DescriptionRegisters Altered Addi Registers Altered Latency RD, rA, rBAndi Logial and with Immediate Andi RD, rA, IMMAndn Logical and notAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMMBeq Branch if Equal BeqBeqd Beqi Branch Immediate if Equal BeqiBeqid Bge Branch if Greater or Equal BgeBged Bgei Branch Immediate if Greater or Equal BgeiBgeid Bgt Branch if Greater Than BgtBgtd Bgti Branch Immediate if Greater Than BgtiBgtid Ble Branch if Less or Equal BleBled Blei Branch Immediate if Less or Equal BleiBleid Blt Branch if Less Than BltBlti BltiBltid Bne Branch if Not Equal BneBned Bnei Branch Immediate if Not Equal BneiBneid Brd Instructions Unconditional BranchBra BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB MsrbipBrki Break Immediate Brki RD, IMMInstructions Barrel Shift Bsrl BsraBsll Bsrai BsiBarrel Shift Immediate Bsrli BslliCmp Integer Compare CmpCmpu Fadd Floating Point Arithmetic Add FaddEsrec FSRIO,UF,OF,DO Frsub Reverse Floating Point Arithmetic SubtractionFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication FmulFdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Nget GetGet from fsl interface CgetIdiv Integer Divide IdivIdivu Imm Immediate ImmIMMLbu Load Byte UnsignedLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMMLhu Lhu RD, rA, rBLhui Load Halfword Unsigned Immediate Lhui RD, rA, IMMLoad Word Lwi Load Word Immediate Lwi RD, rA, IMMMfs Mfs RD, rSMsrclr Read MSR and clear bits in MSR Msrclr RD, ImmMsrset Msrset RD, ImmMts Move To Special Purpose Register Mts RS, rAInstructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMMLogical or Ori Logical or with Immediate Ori RD, rA, IMMPcmpbf Pattern Compare Byte Find PcmpbfPcmpeq Pattern Compare Equal PcmpeqPcmpne Pattern Compare Not Equal PcmpneNput PutPut to fsl interface CputRsubc RsubArithmetic Reverse Subtract Rsub RsubkRsubic RsubiArithmetic Reverse Subtract Immediate Rsubi RsubikRtbd Return from BreakRtbd RA, IMM Rtid Return from Interrupt Rtid RA, IMMMsrie Rted Return from Exception Rted RA, IMMMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMMNone Sbi Store Byte Immediate Sbi RD, rA, IMMSext16 Sext16 RD, rASext8 Sign Extend ByteSext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMMSra Sra RD, rASrc Shift Right with Carry Src RD, rASrl Shift Right LogicalSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMMWdc Write to Data CacheWic Xor Logical Exclusive or Xor RD, rA, rBXori Logical Exclusive or with ImmediateXori RA, rD, IMM 148

Chapter 4: MicroBlaze Instruction Set Architecture

lwi

Load Word Immediate

lwi

rD, rA, IMM

Description

Pseudocode

Registers Altered

Latency

MicroBlaze Processor Reference Guide

UG081 (v6.0) June 1, 2006