Xilinx EDK 8.2i manual General Data Cache Functionality, Data Cache Operation

Data Cache

R

•Cache on and off controlled using a bit in the MSR

•Optional WDC instruction to invalidate data cache lines

General Data Cache Functionality

When the data cache is used, the memory address space in split into two segments: a cacheable segment and a non-cacheable segment. The cacheable area is determined by two parameters: C_DCACHE_BASEADDR and C_DCACHE_HIGHADDR. All addresses within this range correspond to the cacheable address space. All other addresses are non- cacheable.

Data Address Bits

0 30 31

Tag Address

Cache Word Address

- -

Addr	Tag	Tag	=
	BRAM	Valid		Cache_Hit
			Load_Instruction
Addr	Data		Cache_data
	BRAM
Figure 1-10:Data Cache Organization

The cacheable data address consists of two parts: the cache address, and the tag address. The MicroBlaze data cache can be configured from 2kB to 64 kB. This corresponds to a cache address of between 11 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.

For example: in a MicroBlaze configured with C_ICACHE_BASEADDR= 0x00400000, C_ICACHE_HIGHADDR=0x00403fff, C_CACHE_BYTE_SIZE=2048, and C_ICACHE_LINELEN=4; the cacheable memory of 16 kB uses 14 bits of byte address, and the 2 kB cache uses 11 bits of byte address, thus the required address tag width is: 14-11=3 bits. The total number of block RAM primitives required in this configuration is: 1 RAMB16 for storing the 512 instruction words, and 1 RAMB16 for 128 cache line entries, each consisting of: 3 bits of tag, 4 word-valid bits, 1 line-valid bit. In total 2 RAMB16 primitives.

Data Cache Operation

The MicroBlaze data cache implements a write-through protocol. A store to an address within the cacheable range will, provided that the cache is enabled, generate an equivalent byte, halfword, or word write over the data CacheLink (DXCL) to external memory. The write will also update the cached data if the target address word is in the cache (i.e. the write is a cache-hit). A write cache-miss does not load the associated cache line into the cache.

MicroBlaze Processor Reference Guide	www.xilinx.com	39
UG081 (v6.0) June 1, 2006	1-800-255-7778