MicroBlaze Processor Reference Guide
UG081 v6.0 June 1
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
Date Version Revision
UG081 v6.0 June 1
Preface About This Guide
MicroBlaze Application Binary Interface
Manual Contents
Additional Resources
Conventions
Typographical
Online Document
Conventions Meaning or Use Example
UG081 v6.0 June 1
Features
Overview
MicroBlaze Architecture
Version Status Deprecated Active
Data Types and Endianness
Instructions
MSR
ESR
EAR
FSR
Op1 if cond else op2
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
Registers
General Purpose Registers
Special Purpose Registers
Program Counter PC
Registers
8Program Counter PC Bits Name Description Reset Value
Machine Status Register MSR
9Machine Status Register MSR Bits Name Description
PVR
EIP
DCE
ICE
FSL
Buslock Enable
Exception Address Register EAR
Exception Status Register ESR
ESS
Branch Target Register BTR
Source/Destination Register
Floating Point Status Register FSR
Processor Version Register PVR
CFG
Cusebarrel
DIV
Cusediv
Cdebugenabled
OP0EXEC
Unexec
Cunalignedexception
Icll
Cicachelinelen
Icbs
Ccachebytesize
Cresetmsr
Pipeline Architecture
Arch
Rstmsr
Branches
Delay Slots
Memory Architecture
Reset, Interrupts, Exceptions, and Break
Reset, Interrupts, Exceptions, and Break
Reset
Hardware Exceptions
Equivalent Pseudocode
Exception Causes
Breaks
Hardware Breaks
Interrupt
User Vector Exception
Software Breaks
Latency
Instruction Cache
Overview
General Instruction Cache Functionality
Instruction Cache
Data Cache
Instruction Cache Operation
Instruction Cache Software Support
MSR Bit
Data Cache
General Data Cache Functionality
Data Cache Operation
WDC Instruction
Floating Point Unit FPU
Data Cache Software Support
Format
Rounding
Operations
Arithmetic
Hardware Acceleration using FSL
Fast Simplex Link FSL
Exceptions
Comparison
Trace Overview
Debug and Trace
Debug Overview
MicroBlaze Architecture
MicroBlaze I/O Overview
Ilmb
Ixcl
Dxcl
MicroBlaze Signal Interface Description
Dmrnw Dopb
Imrnw Iopb
DAS Dlmb
IAS Ilmb
Mfsl
On-Chip Peripheral Bus OPB Interface Description
Ixclm
Dxcls
Dxclm
LMB Signal Interface
ByteEnable03
Local Memory Bus LMB Interface Description
Addr031
DataWrite031
ReadStrobe
WriteStrobe
DataRead031
Generic Read Operation
LMB Transactions
Generic Write Operation
Back-to-Back Write Operation
Single Cycle Back-to-Back Read Operation
Back-to-Back Mixed Read/Write Operation
BE0 BE1 BE2
RD07 RD815 RD1623 RD2431
Read and Write Data Steering
RD1623 RD2431
Fast Simplex Link FSL Interface Description
Master FSL Signal Interface
Slave FSL Signal Interface
Xilinx CacheLink XCL Interface Description
FSL Transactions
FSL BUS Write Operation
FSL BUS Read Operation
CacheLink Signal Interface
CacheLink Transactions
Data Cache Write
Instruction Cache Read Miss
Data Cache Read Miss
Debug Interface Description
Trace Interface Description
Debug Interface Description
MDM
MicroBlaze Processor Reference Guide
MicroBlaze Core Configurability
11 Type of Trace Exception TraceExceptionKind Description
Values Assigned Type
Cusepcmpinstr
Cusemsrinstr
Pcmpne Cunalignedexception
Cnumberofrdaddrbrk
Cdcacheusefsl
Ffff
Cicacheusefsl
Scope
Data Types
2Register usage conventions Type Enforcement Purpose
Register Usage Conventions
MicroBlaze Application Binary Interface
Stack Convention
Stack Convention
High Memory Low Memory Func
Memory Model
Interrupt and Exception Handling
Notation
1Symbol notation Meaning
Summary
Formats
Type a
Type B
Opcode Destination Reg Source Reg a Immediate Value
Registers Altered
Add
Description
Addi
Registers Altered Latency
RD, rA, rB
Andi
Logial and with Immediate Andi RD, rA, IMM
Andn RD, rA, rB
Andn
Logical and not
Andni
Logical and not with Immediate Andni RD, rA, IMM
Beqd
Beq
Branch if Equal Beq
Beqid
Beqi
Branch Immediate if Equal Beqi
Bged
Bge
Branch if Greater or Equal Bge
Bgeid
Bgei
Branch Immediate if Greater or Equal Bgei
Bgtd
Bgt
Branch if Greater Than Bgt
Bgtid
Bgti
Branch Immediate if Greater Than Bgti
Bled
Ble
Branch if Less or Equal Ble
Bleid
Blei
Branch Immediate if Less or Equal Blei
Blt
Branch if Less Than Blt
Bltid
Blti
Blti
Bned
Bne
Branch if Not Equal Bne
Bneid
Bnei
Branch Immediate if Not Equal Bnei
Instructions Unconditional Branch
Bra
Brd
Brad
MicroBlaze Instruction Set Architecture
Bri
MicroBlaze Instruction Set Architecture
Instructions BrkBreak RD, rB
Msrbip
Brki
Break Immediate Brki RD, IMM
Bsll
Instructions Barrel Shift Bsrl
Bsra
Bsi
Barrel Shift Immediate Bsrli
Bsrai
Bslli
Cmpu
Cmp
Integer Compare Cmp
Esrec FSRIO,UF,OF,DO
Fadd
Floating Point Arithmetic Add Fadd
Frsub RD, rA, rB Reverse subtract
Frsub
Reverse Floating Point Arithmetic Subtraction
Fmul
Floating Point Arithmetic Multiplication Fmul
Fdiv
Floating Point Arithmetic Division
Fdiv RD, rA, rB Divide
Esrec FSRIO,UF,OF,DO,DZ
Fcmp
Esrec FSRIO,DO
Get
Get from fsl interface
Nget
Cget
Idivu
Idiv
Integer Divide Idiv
Imm
Immediate ImmIMM
Lbu RD, rA, rB
Lbu
Load Byte Unsigned
Lbui
Load Byte Unsigned Immediate Lbui RD, rA, IMM
Lhu
Lhu RD, rA, rB
Lhui
Load Halfword Unsigned Immediate Lhui RD, rA, IMM
Load Word
Lwi
Load Word Immediate Lwi RD, rA, IMM
Mfs
Mfs RD, rS
Msrclr
Read MSR and clear bits in MSR Msrclr RD, Imm
Msrset
Msrset RD, Imm
Mts
Move To Special Purpose Register Mts RS, rA
Instructions Mul Multiply RD, rA, rB
Muli
Multiply Immediate Muli RD, rA, IMM
Logical or
Ori
Logical or with Immediate Ori RD, rA, IMM
Pcmpbf
Pattern Compare Byte Find Pcmpbf
Pcmpeq
Pattern Compare Equal Pcmpeq
Pcmpne
Pattern Compare Not Equal Pcmpne
Put
Put to fsl interface
Nput
Cput
Rsub
Arithmetic Reverse Subtract Rsub
Rsubc
Rsubk
Rsubi
Arithmetic Reverse Subtract Immediate Rsubi
Rsubic
Rsubik
Rtbd RA, IMM
Rtbd
Return from Break
Msrie
Rtid
Return from Interrupt Rtid RA, IMM
Msree Msreip ESR
Rted
Return from Exception Rted RA, IMM
Rtsd
Return from Subroutine Rtsd RA, IMM
None
Sbi
Store Byte Immediate Sbi RD, rA, IMM
Sext16
Sext16 RD, rA
Sext8 RD, rA
Sext8
Sign Extend Byte
Instructions Store Halfword RD, rA, rB
Shi
Store Halfword Immediate Shi RD, rA, IMM
Sra
Sra RD, rA
Src
Shift Right with Carry Src RD, rA
Srl RD, rA
Srl
Shift Right Logical
Addr ← rA + rB Addr3031 ← MemAddr ← rD031
Register Altered
Store Word Immediate Swi RD, rA, IMM
Wdc
Write to Data Cache
Wic
Xor
Logical Exclusive or Xor RD, rA, rB
Xori RA, rD, IMM
Xori
Logical Exclusive or with Immediate
148