UG081 v6.0 June 1
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide
Date Version Revision
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
UG081 v6.0 June 1
Preface About This Guide
MicroBlaze Application Binary Interface
Additional Resources
Manual Contents
Typographical
Conventions
Conventions Meaning or Use Example
Online Document
UG081 v6.0 June 1
Overview
Features
Version Status Deprecated Active
MicroBlaze Architecture
Instructions
Data Types and Endianness
ESR
MSR
EAR
FSR
Op1 if cond else op2
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
MicroBlaze Processor Reference Guide
MicroBlaze Processor Reference Guide UG081 v6.0 June 1
Registers
Special Purpose Registers
General Purpose Registers
Program Counter PC
Registers
Machine Status Register MSR
8Program Counter PC Bits Name Description Reset Value
9Machine Status Register MSR Bits Name Description
PVR
DCE
EIP
ICE
FSL
Exception Address Register EAR
Buslock Enable
ESS
Exception Status Register ESR
Source/Destination Register
Branch Target Register BTR
Processor Version Register PVR
Floating Point Status Register FSR
Cusebarrel
CFG
DIV
Cusediv
OP0EXEC
Cdebugenabled
Unexec
Cunalignedexception
Cicachelinelen
Icll
Icbs
Ccachebytesize
Pipeline Architecture
Cresetmsr
Arch
Rstmsr
Branches
Delay Slots
Memory Architecture
Reset, Interrupts, Exceptions, and Break
Reset, Interrupts, Exceptions, and Break
Hardware Exceptions
Reset
Equivalent Pseudocode
Exception Causes
Hardware Breaks
Breaks
User Vector Exception
Interrupt
Software Breaks
Latency
Overview
Instruction Cache
General Instruction Cache Functionality
Instruction Cache
Instruction Cache Operation
Data Cache
Instruction Cache Software Support
MSR Bit
Data Cache
General Data Cache Functionality
Data Cache Operation
WDC Instruction
Floating Point Unit FPU
Data Cache Software Support
Rounding
Format
Operations
Arithmetic
Fast Simplex Link FSL
Hardware Acceleration using FSL
Exceptions
Comparison
Trace Overview
Debug and Trace
Debug Overview
MicroBlaze Architecture
Ilmb
MicroBlaze I/O Overview
Ixcl
Dxcl
Dmrnw Dopb
MicroBlaze Signal Interface Description
DAS Dlmb
Imrnw Iopb
IAS Ilmb
Mfsl
Ixclm
On-Chip Peripheral Bus OPB Interface Description
Dxcls
Dxclm
ByteEnable03
LMB Signal Interface
Local Memory Bus LMB Interface Description
Addr031
ReadStrobe
DataWrite031
WriteStrobe
DataRead031
Generic Read Operation
LMB Transactions
Generic Write Operation
Single Cycle Back-to-Back Read Operation
Back-to-Back Write Operation
Back-to-Back Mixed Read/Write Operation
BE0 BE1 BE2
RD07 RD815 RD1623 RD2431
Read and Write Data Steering
RD1623 RD2431
Fast Simplex Link FSL Interface Description
Master FSL Signal Interface
Slave FSL Signal Interface
FSL Transactions
Xilinx CacheLink XCL Interface Description
FSL BUS Write Operation
FSL BUS Read Operation
CacheLink Signal Interface
CacheLink Transactions
Data Cache Write
Instruction Cache Read Miss
Data Cache Read Miss
Trace Interface Description
Debug Interface Description
Debug Interface Description
MDM
MicroBlaze Processor Reference Guide
11 Type of Trace Exception TraceExceptionKind Description
MicroBlaze Core Configurability
Values Assigned Type
Cusemsrinstr
Cusepcmpinstr
Pcmpne Cunalignedexception
Cnumberofrdaddrbrk
Cdcacheusefsl
Ffff
Cicacheusefsl
Data Types
Scope
2Register usage conventions Type Enforcement Purpose
Register Usage Conventions
MicroBlaze Application Binary Interface
Stack Convention
Stack Convention
High Memory Low Memory Func
Memory Model
Interrupt and Exception Handling
Notation
1Symbol notation Meaning
Summary
Type a
Formats
Type B
Opcode Destination Reg Source Reg a Immediate Value
Registers Altered
Add
Description
Addi
RD, rA, rB
Registers Altered Latency
Logial and with Immediate Andi RD, rA, IMM
Andi
Andn RD, rA, rB
Andn
Logical and not
Logical and not with Immediate Andni RD, rA, IMM
Andni
Beqd
Beq
Branch if Equal Beq
Beqid
Beqi
Branch Immediate if Equal Beqi
Bged
Bge
Branch if Greater or Equal Bge
Bgeid
Bgei
Branch Immediate if Greater or Equal Bgei
Bgtd
Bgt
Branch if Greater Than Bgt
Bgtid
Bgti
Branch Immediate if Greater Than Bgti
Bled
Ble
Branch if Less or Equal Ble
Bleid
Blei
Branch Immediate if Less or Equal Blei
Branch if Less Than Blt
Blt
Bltid
Blti
Blti
Bned
Bne
Branch if Not Equal Bne
Bneid
Bnei
Branch Immediate if Not Equal Bnei
Bra
Instructions Unconditional Branch
Brd
Brad
MicroBlaze Instruction Set Architecture
Bri
MicroBlaze Instruction Set Architecture
Msrbip
Instructions BrkBreak RD, rB
Break Immediate Brki RD, IMM
Brki
Bsll
Instructions Barrel Shift Bsrl
Bsra
Barrel Shift Immediate Bsrli
Bsi
Bsrai
Bslli
Cmpu
Cmp
Integer Compare Cmp
Esrec FSRIO,UF,OF,DO
Fadd
Floating Point Arithmetic Add Fadd
Frsub RD, rA, rB Reverse subtract
Frsub
Reverse Floating Point Arithmetic Subtraction
Floating Point Arithmetic Multiplication Fmul
Fmul
Floating Point Arithmetic Division
Fdiv
Fdiv RD, rA, rB Divide
Esrec FSRIO,UF,OF,DO,DZ
Fcmp
Esrec FSRIO,DO
Get from fsl interface
Get
Nget
Cget
Idivu
Idiv
Integer Divide Idiv
Immediate ImmIMM
Imm
Lbu RD, rA, rB
Lbu
Load Byte Unsigned
Load Byte Unsigned Immediate Lbui RD, rA, IMM
Lbui
Lhu RD, rA, rB
Lhu
Load Halfword Unsigned Immediate Lhui RD, rA, IMM
Lhui
Load Word
Load Word Immediate Lwi RD, rA, IMM
Lwi
Mfs RD, rS
Mfs
Read MSR and clear bits in MSR Msrclr RD, Imm
Msrclr
Msrset RD, Imm
Msrset
Move To Special Purpose Register Mts RS, rA
Mts
Instructions Mul Multiply RD, rA, rB
Multiply Immediate Muli RD, rA, IMM
Muli
Logical or
Logical or with Immediate Ori RD, rA, IMM
Ori
Pattern Compare Byte Find Pcmpbf
Pcmpbf
Pattern Compare Equal Pcmpeq
Pcmpeq
Pattern Compare Not Equal Pcmpne
Pcmpne
Put to fsl interface
Put
Nput
Cput
Arithmetic Reverse Subtract Rsub
Rsub
Rsubc
Rsubk
Arithmetic Reverse Subtract Immediate Rsubi
Rsubi
Rsubic
Rsubik
Rtbd RA, IMM
Rtbd
Return from Break
Msrie
Rtid
Return from Interrupt Rtid RA, IMM
Msree Msreip ESR
Rted
Return from Exception Rted RA, IMM
Return from Subroutine Rtsd RA, IMM
Rtsd
None
Store Byte Immediate Sbi RD, rA, IMM
Sbi
Sext16 RD, rA
Sext16
Sext8 RD, rA
Sext8
Sign Extend Byte
Instructions Store Halfword RD, rA, rB
Store Halfword Immediate Shi RD, rA, IMM
Shi
Sra RD, rA
Sra
Shift Right with Carry Src RD, rA
Src
Srl RD, rA
Srl
Shift Right Logical
Addr ← rA + rB Addr3031 ← MemAddr ← rD031
Store Word Immediate Swi RD, rA, IMM
Register Altered
Write to Data Cache
Wdc
Wic
Logical Exclusive or Xor RD, rA, rB
Xor
Xori RA, rD, IMM
Xori
Logical Exclusive or with Immediate
148