Xilinx EDK MicroBlaze Signal Interface Description and Fast Simplex Link Overview

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Chapter 2: MicroBlaze Signal Interface Description

Fast Simplex Link (FSL) Interface Description

The Fast Simplex Link bus provides a point-to-point communication channel between an output FIFO and an input FIFO. For details on the generic FSL protocol please refer to the “Fast Simplex Link (FSL) bus” data sheet (DS449).

Master FSL Signal Interface

MicroBlaze may contain up to 8 master FSL interfaces. The master signals are depicted in Table 2-6.

Table 2-6:Master FSL signals

Signal Name	Description	VHDL Type	Direction
FSLn_M_Clk	Clock	std_logic	input
FSLn_M_Write	Write enable signal	std_logic	output
	indicating that data is being
	written to the output FSL
FSLn_M_Data	Data value written to the	std_logic_vector	output
	output FSL
FSLn_M_Control	Control bit value written to	std_logic	output
	the output FSL
FSLn_M_Full	Full Bit indicating output	std_logic	input
	FSL FIFO is full when set

Slave FSL Signal Interface

MicroBlaze may contain up to 8 slave FSL interfaces. The slave FSL interface signals are depicted in Table 2-7.

Table 2-7:Slave FSL signals

Signal Name	Description	VHDL Type	Direction
FSLn_S_Clk	Clock	std_logic	input
FSLn_S_Read	Read acknowledge signal	std_logic	output
	indicating that data has been
	read from the input FSL
FSLn_S_Data	Data value currently	std_logic_vector	input
	available at the top of the
	input FSL
FSLn_S_Control	Control Bit value currently	std_logic	input
	available at the top of the
	input FSL
FSLn_S_Exists	Flag indicating that data	std_logic	input
	exists in the input FSL

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