General Purpose Registers, Program Counter PC | Xilinx EDK 8.2i

Registers

R

General Purpose Registers

The thirty-two 32-bit General Purpose Registers are numbered R0 through R31. The register ﬁle is reset on bit stream download (reset value is 0x00000000).

Note: The register ﬁle is not reset by the external reset inputs: reset and debug_rst.

031

↑

	R0-R31
	Figure 1-2:	R0-R31
Table 1-7:General Purpose Registers (R0-R31)

Bits	Name	Description	Reset Value

0:31	R0	R0 is deﬁned to always have the value	0x00000000
		of zero. Anything written to R0 is
		discarded.

0:31	R1 through R13	R1 through R13 are 32-bit general	-
		purpose registers

0:31	R14	32-bit used to store return addresses	-
		for interrupts

0:31	R15	32-bit general purpose register	-

0:31	R16	32-bit used to store return addresses	-
		for breaks

0:31	R17	If MicroBlaze is conﬁgured to support	-
		hardware exceptions, this register is
		loaded with HW exception return
		address (see also “Branch Target
		Register (BTR)”); if not it is a general
		purpose register

0:31	R18 through R31	R18 through R31 are 32-bit general	-
		purpose registers.

Please refer to Table 3-2for software conventions on general purpose register usage.

Special Purpose Registers

Program Counter (PC)

The Program Counter is the 32-bit address of the execution instruction. It can be read with an MFS instruction, but it can not be written to using an MTS instruction. When used with the MFS instruction the PC register is speciﬁed by setting Sa = 0x0000.

MicroBlaze Processor Reference Guide	www.xilinx.com	21
UG081 (v6.0) June 1, 2006	1-800-255-7778

Image 21

Xilinx EDK 8.2i manual General Purpose Registers, Special Purpose Registers, Program Counter PC

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness ESR MSREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Special Purpose Registers General Purpose RegistersProgram Counter PC Registers Machine Status Register MSR 8Program Counter PC Bits Name Description Reset Value9Machine Status Register MSR Bits Name Description PVR DCE EIPICE FSL Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusebarrel CFGDIV Cusediv OP0EXEC CdebugenabledUnexec Cunalignedexception Cicachelinelen IcllIcbs Ccachebytesize Pipeline Architecture CresetmsrArch Rstmsr Delay Slots Memory ArchitectureBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Hardware Exceptions ResetEquivalent Pseudocode Exception Causes Hardware Breaks Breaks User Vector Exception InterruptSoftware Breaks Latency Overview Instruction CacheGeneral Instruction Cache Functionality Instruction Cache Instruction Cache Operation Data CacheInstruction Cache Software Support MSR Bit General Data Cache Functionality Data Cache OperationData Cache Floating Point Unit FPU Data Cache Software SupportWDC Instruction Rounding FormatOperations Arithmetic Fast Simplex Link FSL Hardware Acceleration using FSLExceptions Comparison Debug and Trace Debug OverviewTrace Overview MicroBlaze Architecture Ilmb MicroBlaze I/O OverviewIxcl Dxcl Dmrnw Dopb MicroBlaze Signal Interface Description DAS Dlmb Imrnw IopbIAS Ilmb Mfsl Ixclm On-Chip Peripheral Bus OPB Interface DescriptionDxcls Dxclm ByteEnable03 LMB Signal InterfaceLocal Memory Bus LMB Interface Description Addr031 ReadStrobe DataWrite031WriteStrobe DataRead031 LMB Transactions Generic Write OperationGeneric Read Operation Single Cycle Back-to-Back Read Operation Back-to-Back Write OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 Read and Write Data Steering RD1623 RD2431RD07 RD815 RD1623 RD2431 Master FSL Signal Interface Slave FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL Transactions Xilinx CacheLink XCL Interface DescriptionFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read MissData Cache Write Trace Interface Description Debug Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cusemsrinstr CusepcmpinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Ffff CicacheusefslCdcacheusefsl Data Types Scope Register Usage Conventions MicroBlaze Application Binary Interface2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling 1Symbol notation Meaning SummaryNotation Type a FormatsType B Opcode Destination Reg Source Reg a Immediate Value Add DescriptionRegisters Altered Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Andn Logical and notAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM Andni Beq Branch if Equal BeqBeqd Beqi Branch Immediate if Equal BeqiBeqid Bge Branch if Greater or Equal BgeBged Bgei Branch Immediate if Greater or Equal BgeiBgeid Bgt Branch if Greater Than BgtBgtd Bgti Branch Immediate if Greater Than BgtiBgtid Ble Branch if Less or Equal BleBled Blei Branch Immediate if Less or Equal BleiBleid Branch if Less Than Blt Blt Blti BltiBltid Bne Branch if Not Equal BneBned Bnei Branch Immediate if Not Equal BneiBneid Bra Instructions Unconditional BranchBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Instructions Barrel Shift Bsrl BsraBsll Barrel Shift Immediate Bsrli BsiBsrai Bslli Cmp Integer Compare CmpCmpu Fadd Floating Point Arithmetic Add FaddEsrec FSRIO,UF,OF,DO Frsub Reverse Floating Point Arithmetic SubtractionFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul Fmul Floating Point Arithmetic Division FdivFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get from fsl interface GetNget Cget Idiv Integer Divide IdivIdivu Immediate ImmIMM Imm Lbu Load Byte UnsignedLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Put to fsl interface PutNput Cput Arithmetic Reverse Subtract Rsub RsubRsubc Rsubk Arithmetic Reverse Subtract Immediate Rsubi RsubiRsubic Rsubik Rtbd Return from BreakRtbd RA, IMM Rtid Return from Interrupt Rtid RA, IMMMsrie Rted Return from Exception Rted RA, IMMMsree Msreip ESR Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sext8 Sign Extend ByteSext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Srl Shift Right LogicalSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Xori Logical Exclusive or with ImmediateXori RA, rD, IMM 148