Xilinx EDK 8.2i

MicroBlaze Processor Reference Guide www.xilinx.com 23

UG081 (v6.0) June 1, 2006 1-800-255-7778

Registers R

22 EIP Exception In Progress

0 No hardware exception in progress

1 Hardware exception in progress

Read/Write

23 EE Exception Enable

0 Hardware exceptions disabled

1 Hardware exceptions enabled

Read/Write

24 DCE Data Cache Enable

0 Data Cache is Disabled

1 Data Cache is Enabled

Read/Write

25 DZ Division by Zero1

0 No division by zero has occurred

1 Division by zero has occurred

Read/Write

26 ICE Instruction Cache Enable

0 Instruction Cache is Disabled

1 Instruction Cache is Enabled

Read/Write

27 FSL FSL Error

0 FSL get/put had no error

1 FSL get/put had mismatch in

control type

Read/Write

28 BIP Break in Progress

0 No Break in Progress

1 Break in Progress

Sourceof break can be software break

instruction or hardware break from

Ext_Brk or Ext_NM_Brk pin.

Read/Write

Table 1-9: Machine Status Register (MSR) (Continued)

Bits Name Description Reset Value

Contents

Main Page MicroBlaze Processor Reference Guide UG081 (v6.0) June 1, 2006 Page Preface: About This Guide Chapter 1: MicroBlaze Architecture Chapter 2: MicroBlaze Signal Interface Description Chapter 3: MicroBlaze Application Binary Interface Chapter 4: MicroBlaze Instruction Set Architecture Preface About This Guide Manual Contents Additional Resources Conventions Typographical Online Document Page Chapter 1 MicroBlaze Architecture Overview Features Page Data Types and Endianness Instructions Page Page Page Page Page Page Registers General Purpose Registers Special Purpose Registers Program Counter (PC) Machine Status Register (MSR) Page Exception Address Register (EAR) Exception Status Register (ESR) Branch Target Register (BTR) Floating Point Status Register (FSR) Processor Version Register (PVR) Page Page Page Pipeline Architecture Branches Delay Slots Memory Architecture Reset, Interrupts, Exceptions, and Break Reset Hardware Exceptions Exception Causes Breaks Hardware Breaks Software Breaks Interrupt User Vector (Exception) Instruction Cache General Instruction Cache Functionality BRAM Tag Instruction Cache Operation Data Cache General Data Cache Functionality Data Cache Operation Tag BRAM Data Cache Software Support Floating Point Unit (FPU) Format Rounding Operations Arithmetic Comparison Fast Simplex Link (FSL) Hardware Acceleration using FSL Debug and Trace Debug Overview Trace Overview f Page Chapter 2 MicroBlaze Signal Interface Description Overview Features MicroBlaze I/O Overview Page Page On-Chip Peripheral Bus (OPB) Interface Description Local Memory Bus (LMB) Interface Description LMB Signal Interface Addr[0:31] Byte_Enable[0:3] Page LMB Transactions Generic Write Operation Generic Read Operation Back-to-Back Write Operation Single Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation Read and Write Data Steering Fast Simplex Link (FSL) Interface Description Master FSL Signal Interface Slave FSL Signal Interface FSL Transactions FSL BUS Write Operation Xilinx CacheLink (XCL) Interface Description CacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read Miss Data Cache Write Debug Interface Description Trace Interface Description Page MicroBlaze Core Congurability Page Page Page Chapter 3 MicroBlaze Application Binary Interface Scope Data Types Register Usage Conventions Stack Convention Page Calling Convention Memory Model Small data area Data area Common un-initialized area Literals or constants Interrupt and Exception Handling Chapter 4 MicroBlaze Instruction Set Architecture Summary Notation Formats Type A Type B Instructions add addi and andi andn andni beq beqi bge bgei bgt bgti ble blei blt blti bne bnei br Page bri Page brk brki bs bsi cmp Chapter 4: MicroBlaze Instruction Set Architecture fadd This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1. The oating point sum of registers rA and rB, is placed into register rD. 4 cycles fadd rD, rA, rB Add frsub fmul MicroBlaze Processor Reference Guide www.xilinx.com 103 UG081 (v6.0) June 1, 2006 1-800-255-7778 Instructions fdiv This instruction is only available when the MicroBlaze parameter C_USE_FPU is set to 1. 28 cycles fdiv rD, rA, rB Divide 0 1 0 1 1 0 rD rA rB 0 0 1 1 0 0 0 0 0 0 0 0 6 11 16 21 31 fcmp Page get idiv imm lbu lbui lhu lhui lw lwi mfs msrclr msrset mts mul muli or ori pcmpbf pcmpeq pcmpne put rsub rsubi rtbd rtid rted rtsd sb sbi sext16 sext8 sh shi sra src srl sw swi wdc wic xor xori