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Xilinx EDK 8.2i manual Summary, Notation, 1Symbol notation Meaning

Models: EDK 8.2i

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Chapter 4

MicroBlaze Instruction Set Architecture

Summary

This chapter provides a detailed guide to the Instruction Set Architecture of MicroBlaze™.

Notation

The symbols used throughout this document are deﬁned in Table 4-1.

Table 4-1:Symbol notation

Symbol			Meaning

+			Add

-			Subtract

×			Multiply

∧			Bitwise logical AND

∨			Bitwise logical OR

⊕			Bitwise logical XOR

			Bitwise logical complement of x
	x

←			Assignment

>>			Right shift

<<			Left shift

rx			Register x

x[i]			Bit i in register x

x[i:j]			Bits i through j in register x

=			Equal comparison

≠			Not equal comparison

>			Greater than comparison

>=			Greater than or equal comparison

<			Less than comparison

<=			Less than or equal comparison

sext(x)			Sign-extend x

MicroBlaze Processor Reference Guide	www.xilinx.com	71
UG081 (v6.0) June 1, 2006	1-800-255-7778

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Xilinx EDK 8.2i manual Summary, Notation, 1Symbol notation Meaning

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference GuideMicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual ContentsTypographical ConventionsConventions Meaning or Use Example Online DocumentUG081 v6.0 June 1 Overview FeaturesVersion Status Deprecated Active MicroBlaze ArchitectureInstructions Data Types and EndiannessFSR MSRESR EAROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PCPVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name DescriptionFSL EIPDCE ICEException Address Register EAR Buslock EnableESS Exception Status Register ESRSource/Destination Register Branch Target Register BTRProcessor Version Register PVR Floating Point Status Register FSRCusediv CFGCusebarrel DIVCunalignedexception CdebugenabledOP0EXEC UnexecCcachebytesize IcllCicachelinelen IcbsRstmsr CresetmsrPipeline Architecture ArchBranches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakException Causes ResetHardware Exceptions Equivalent PseudocodeHardware Breaks BreaksLatency InterruptUser Vector Exception Software BreaksInstruction Cache Instruction CacheOverview General Instruction Cache FunctionalityMSR Bit Data CacheInstruction Cache Operation Instruction Cache Software SupportData Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Arithmetic FormatRounding OperationsComparison Hardware Acceleration using FSLFast Simplex Link FSL ExceptionsTrace Overview Debug and TraceDebug Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb IxclDmrnw Dopb MicroBlaze Signal Interface DescriptionMfsl Imrnw IopbDAS Dlmb IAS IlmbDxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm DxclsAddr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface DescriptionDataRead031 DataWrite031ReadStrobe WriteStrobeGeneric Read Operation LMB TransactionsGeneric Write Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write OperationRD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write OperationCacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss MDM Debug Interface DescriptionTrace Interface Description Debug Interface DescriptionMicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core ConﬁgurabilityValues Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne CunalignedexceptionCdcacheusefsl FfffCicacheusefsl Data Types Scope2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type BRegisters Altered AddDescription Addi RD, rA, rB Registers Altered LatencyLogial and with Immediate Andi RD, rA, IMM AndiAndn RD, rA, rB AndnLogical and not Logical and not with Immediate Andni RD, rA, IMM AndniBeqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Branch if Less Than Blt BltBltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Brad Instructions Unconditional BranchBra BrdMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rBBreak Immediate Brki RD, IMM BrkiBsll Instructions Barrel Shift BsrlBsra Bslli BsiBarrel Shift Immediate Bsrli BsraiCmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Floating Point Arithmetic Multiplication Fmul FmulEsrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB DivideFcmp Esrec FSRIO,DO Cget GetGet from fsl interface NgetIdivu IdivInteger Divide Idiv Immediate ImmIMM ImmLbu RD, rA, rB LbuLoad Byte Unsigned Load Byte Unsigned Immediate Lbui RD, rA, IMM LbuiLhu RD, rA, rB LhuLoad Halfword Unsigned Immediate Lhui RD, rA, IMM LhuiLoad Word Load Word Immediate Lwi RD, rA, IMM LwiMfs RD, rS MfsRead MSR and clear bits in MSR Msrclr RD, Imm MsrclrMsrset RD, Imm MsrsetMove To Special Purpose Register Mts RS, rA MtsInstructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM MuliLogical or Logical or with Immediate Ori RD, rA, IMM OriPattern Compare Byte Find Pcmpbf PcmpbfPattern Compare Equal Pcmpeq PcmpeqPattern Compare Not Equal Pcmpne PcmpneCput PutPut to fsl interface NputRsubk RsubArithmetic Reverse Subtract Rsub RsubcRsubik RsubiArithmetic Reverse Subtract Immediate Rsubi RsubicRtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Return from Subroutine Rtsd RA, IMM RtsdNone Store Byte Immediate Sbi RD, rA, IMM SbiSext16 RD, rA Sext16Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM ShiSra RD, rA SraShift Right with Carry Src RD, rA SrcSrl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register AlteredWrite to Data Cache WdcWic Logical Exclusive or Xor RD, rA, rB XorXori RA, rD, IMM XoriLogical Exclusive or with Immediate 148