Xilinx EDK 8.2i manual Floating Point Unit FPU, Data Cache Software Support, WDC Instruction

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Chapter 1: MicroBlaze Architecture

A load from an address within the cacheable range will, provided that the cache is enabled, trigger a check to determine if the requested data is currently cached. If it is (i.e. on a cache- hit) the requested data is retrieved from the cache. If not (i.e. on a cache-miss) the address is requested over data CacheLink (DXCL), and the processor pipeline will stall until the cache line associated to the requested address is returned from the external memory controller.

Data Cache Software Support

MSR Bit

The DCE bit in the MSR controls whether or not the cache is enabled. When disabling caches the user must ensure that all the prior writes within the cacheable range has been completed in external memory before reading back over OPB. This can be done by writing to a semaphore immediately before turning off caches, and then in a loop poll the semaphore until it has been written.

The contents of the cache is preserved when the cache is disabled.

WDC Instruction

The optional WDC instruction (C_ALLOW_DCACHE_WR=1) is used to invalidate cache lines in the data cache from an application. For a detailed description, please refer to Chapter 4, “MicroBlaze Instruction Set Architecture”.

Floating Point Unit (FPU)

Overview

The MicroBlaze floating point unit is based on the IEEE 754 standard:

•Uses IEEE 754 single precision floating point format, including definitions for infinity, not-a-number (NaN), and zero

•Supports addition, subtraction, multiplication, division, and comparison instructions

•Implements round-to-nearest mode

•Generates sticky status bits for: underflow, overflow, and invalid operation

For improved performance, the following non-standard simplifications are made:

•Denormalized(1) operands are not supported. A hardware floating point operation on a denormalized number will return a quiet NaN and set the denormalized operand error bit in FSR; see "Floating Point Status Register (FSR)" on page 27

•A denormalized result is stored as a signed 0 with the underflow bit set in FSR. This method is commonly referred to as Flush-to-Zero (FTZ)

•An operation on a quiet NaN will return the fixed NaN: 0xFFC00000, rather than one of the NaN operands

•Overflow as a result of a floating point operation will always return signed ∞, even when the exception is trapped.

1.Numbers that are so close to 0, that they cannot be represented with full precision, i.e. any number n that falls in the following ranges: ( 1.17549*10-38> n > 0 ), or ( 0 > n > -1.17549 * 10-38)

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