Store Halfword Immediate Shi RD, rA, IMM

Chapter 4: MicroBlaze Instruction Set Architecture

shi

Store Halfword Immediate

shi	rD, rA, IMM

1 1 1 1 0 1

IMM

Description

Stores the contents of the least signiﬁcant halfword of register rD, into the halfword aligned memory location that results from adding the contents of register rA and the value IMM, sign-extended to 32 bits.

Pseudocode

Addr ← (rA) + sext(IMM)

Addr[31] ← 0

Mem(Addr) ← ( rD)[16:31]

Registers Altered

•ESR [S]

Latency

1 cycle

Note

By default, Type B Instructions will take the 16-bit IMM ﬁeld value and sign extend it to 32 bits to use as the immediate operand. This behavior can be overridden by preceding the Type B instruction with an imm instruction. See the imm instruction for details on using 32-bit immediate values.

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Xilinx EDK 8.2i manual Store Halfword Immediate Shi RD, rA, IMM

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions EAR MSRESR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers 9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVR ICE EIPDCE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR DIV CFGCusebarrel Cusediv Unexec CdebugenabledOP0EXEC Cunalignedexception Icbs IcllCicachelinelen Ccachebytesize Arch CresetmsrPipeline Architecture Rstmsr Delay Slots Memory ArchitectureBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Equivalent Pseudocode ResetHardware Exceptions Exception Causes Breaks Hardware Breaks Software Breaks InterruptUser Vector Exception Latency General Instruction Cache Functionality Instruction CacheOverview Instruction Cache Instruction Cache Software Support Data CacheInstruction Cache Operation MSR Bit General Data Cache Functionality Data Cache OperationData Cache Floating Point Unit FPU Data Cache Software SupportWDC Instruction Operations FormatRounding Arithmetic Exceptions Hardware Acceleration using FSLFast Simplex Link FSL Comparison Debug and Trace Debug OverviewTrace Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb IAS Ilmb Imrnw IopbDAS Dlmb Mfsl Dxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxclm Local Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031 WriteStrobe DataWrite031ReadStrobe DataRead031 LMB Transactions Generic Write OperationGeneric Read Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2 Read and Write Data Steering RD1623 RD2431RD07 RD815 RD1623 RD2431 Master FSL Signal Interface Slave FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Instruction Cache Read Miss Data Cache Read MissData Cache Write Debug Interface Description Debug Interface DescriptionTrace Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr Cnumberofrdaddrbrk Ffff CicacheusefslCdcacheusefsl Scope Data Types Register Usage Conventions MicroBlaze Application Binary Interface2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling 1Symbol notation Meaning SummaryNotation Type B FormatsType a Opcode Destination Reg Source Reg a Immediate Value Add DescriptionRegisters Altered Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Andn Logical and notAndn RD, rA, rB Andni Logical and not with Immediate Andni RD, rA, IMM Beq Branch if Equal BeqBeqd Beqi Branch Immediate if Equal BeqiBeqid Bge Branch if Greater or Equal BgeBged Bgei Branch Immediate if Greater or Equal BgeiBgeid Bgt Branch if Greater Than BgtBgtd Bgti Branch Immediate if Greater Than BgtiBgtid Ble Branch if Less or Equal BleBled Blei Branch Immediate if Less or Equal BleiBleid Blt Branch if Less Than Blt Blti BltiBltid Bne Branch if Not Equal BneBned Bnei Branch Immediate if Not Equal BneiBneid Brd Instructions Unconditional BranchBra Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Instructions Barrel Shift Bsrl BsraBsll Bsrai BsiBarrel Shift Immediate Bsrli Bslli Cmp Integer Compare CmpCmpu Fadd Floating Point Arithmetic Add FaddEsrec FSRIO,UF,OF,DO Frsub Reverse Floating Point Arithmetic SubtractionFrsub RD, rA, rB Reverse subtract Fmul Floating Point Arithmetic Multiplication Fmul Fdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Nget GetGet from fsl interface Cget Idiv Integer Divide IdivIdivu Imm Immediate ImmIMM Lbu Load Byte UnsignedLbu RD, rA, rB Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Nput PutPut to fsl interface Cput Rsubc RsubArithmetic Reverse Subtract Rsub Rsubk Rsubic RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubik Rtbd Return from BreakRtbd RA, IMM Rtid Return from Interrupt Rtid RA, IMMMsrie Rted Return from Exception Rted RA, IMMMsree Msreip ESR Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sext8 Sign Extend ByteSext8 RD, rA Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Srl Shift Right LogicalSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Xori Logical Exclusive or with ImmediateXori RA, rD, IMM 148

Chapter 4: MicroBlaze Instruction Set Architecture

shi

Store Halfword Immediate

shi

rD, rA, IMM

Description

Pseudocode

Registers Altered

Latency

MicroBlaze Processor Reference Guide

UG081 (v6.0) June 1, 2006