MicroBlaze Core Configurability

Table 2-12:MPD Parameters

R

Parameter Name

Feature/Description

Allowable

Default

EDK Tool

VHDL

Values

Value

Assigned

Type

 

 

 

 

 

 

 

 

C_USE_FPU

Include hardware floating

0, 1

0

 

integer

 

point unit (Virtex2 and

 

 

 

 

 

later)

 

 

 

 

 

 

 

 

 

 

C_USE_MSR_INSTR

Enable use of instructions:

1

1

 

integer

 

MSRSET and MSRCLR

 

 

 

 

 

 

 

 

 

 

C_USE_PCMP_INSTR

Enable use of instructions:

1

1

 

integer

 

PCMPBF, PCMPEQ, and

 

 

 

 

 

PCMPNE

 

 

 

 

 

 

 

 

 

 

C_UNALIGNED_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for unaligned data

 

 

 

 

 

accesses

 

 

 

 

 

 

 

 

 

 

C_ILL_OPCODE_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for illegal op-code

 

 

 

 

 

 

 

 

 

 

C_IOPB_BUS_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for IOPB bus error

 

 

 

 

 

 

 

 

 

 

C_DOPB_BUS_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for DOPB bus error

 

 

 

 

 

 

 

 

 

 

C_DIV_ZERO_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for division by zero

 

 

 

 

 

 

 

 

 

 

C_FPU_EXCEPTION

Enable exception handling

0, 1

0

 

integer

 

for hardware floating

 

 

 

 

 

point unit exceptions

 

 

 

 

 

 

 

 

 

 

C_OPCODE_0x0_ILLEGAL

Detect opcode 0x0 as an

0,1

0

 

integer

 

illegal instruction

 

 

 

 

 

 

 

 

 

 

C_DEBUG_ENABLED

MDM Debug interface

0,1

0

 

integer

 

 

 

 

 

 

C_NUMBER_OF_PC_BRK

Number of hardware

0-8

1

 

integer

 

breakpoints

 

 

 

 

 

 

 

 

 

 

C_NUMBER_OF_RD_ADDR_BRK

Number of read address

0-4

0

 

integer

 

watchpoints

 

 

 

 

 

 

 

 

 

 

C_NUMBER_OF_WR_ADDR_BRK

Number of write address

0-4

0

 

integer

 

watchpoints

 

 

 

 

 

 

 

 

 

 

C_INTERRUPT_IS_EDGE

Level/Edge Interrupt

0, 1

0

 

integer

 

 

 

 

 

 

C_EDGE_IS_POSITIVE

Negative/Positive Edge

0, 1

1

 

integer

 

Interrupt

 

 

 

 

 

 

 

 

 

 

C_FSL_LINKS

Number of FSL interfaces

0-8

0

yes

integer

 

 

 

 

 

 

C_FSL_DATA_SIZE

FSL data bus size

32

32

NA

integer

 

 

 

 

 

 

C_ICACHE_BASEADDR

Instruction cache base

0x00000000 -

0x0000

 

std_logi

 

address

0xFFFFFFFF

0000

 

c_vector

 

 

 

 

 

 

MicroBlaze Processor Reference Guide

www.xilinx.com

63

UG081 (v6.0) June 1, 2006

1-800-255-7778

 

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Xilinx EDK 8.2i manual Cusemsrinstr, Cusepcmpinstr, Pcmpne Cunalignedexception, Cnumberofrdaddrbrk, Cnumberofwraddrbrk