Xilinx EDK 8.2i manual Branch if Less Than Blt

Instructions

blt	Branch if Less Than
	blt	rA, rB	Branch if Less Than
	bltd	rA, rB	Branch if Less Than with Delay

R

1 0 0 1 1 1

D 0 0 1 0

rA

rB

0 0 0 0 0 0 0 0 0 0 0

0 6 11 16 21 31

Description

Branch if rA is less than 0, to the instruction located in the offset value of rB. The target of the branch will be the instruction at address PC + rB.

The mnemonic bltd will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (i.e. in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

Pseudocode

If rA < 0 then PC ← PC + rB

else

PC ← PC + 4 if D = 1 then

allow following instruction to complete execution

Registers Altered

•PC

Latency

1 cycle (if branch is not taken)

2 cycles (if branch is taken and the D bit is set)

3 cycles (if branch is taken and the D bit is not set)

Note

A delay slot must not be used by the following: IMM, branch, or break instructions. This also applies to instructions causing recoverable exceptions (e.g. unalignement), when hardware exceptions are enabled. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.

MicroBlaze Processor Reference Guide	www.xilinx.com	87
UG081 (v6.0) June 1, 2006	1-800-255-7778