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Xilinx EDK 8.2i manual Read MSR and clear bits in MSR Msrclr RD, Imm

Models: EDK 8.2i

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Chapter 4: MicroBlaze Instruction Set Architecture

msrclr

Read MSR and clear bits in MSR

msrclr

rD, Imm

1 0 0 1 0 1

0 0 0 0 1

0 0

Imm14

16 17 18

Description

Copies the contents of the special purpose register MSR into register rD.

Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched.

Pseudocode

(rD) ← (MSR)

(MSR) ← (MSR) ∧ ( IMM))

Registers Altered

•rD

•MSR

Latency

1 cycle

Note

MSRCLR will affect some MSR bits immediately (e.g. Carry) while the remaining bits will take effect one cycle after the instruction has been executed.

The immediate values has to be less than 214. Only bits 18 to 31 of the MSR can be cleared.

116	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Page 116

Image 116

Xilinx EDK 8.2i manual Read MSR and clear bits in MSR Msrclr RD, Imm

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version RevisionUG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional ResourcesConventions TypographicalOnline Document Conventions Meaning or Use ExampleUG081 v6.0 June 1 Features OverviewMicroBlaze Architecture Version Status Deprecated ActiveData Types and Endianness InstructionsMSR ESREAR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers General Purpose Registers Special Purpose RegistersProgram Counter PC Registers8Program Counter PC Bits Name Description Reset Value Machine Status Register MSR9Machine Status Register MSR Bits Name Description PVREIP DCEICE FSLBuslock Enable Exception Address Register EARException Status Register ESR ESSBranch Target Register BTR Source/Destination RegisterFloating Point Status Register FSR Processor Version Register PVRCFG CusebarrelDIV CusedivCdebugenabled OP0EXECUnexec CunalignedexceptionIcll CicachelinelenIcbs CcachebytesizeCresetmsr Pipeline ArchitectureArch RstmsrBranches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakReset Hardware ExceptionsEquivalent Pseudocode Exception CausesBreaks Hardware BreaksInterrupt User Vector ExceptionSoftware Breaks LatencyInstruction Cache OverviewGeneral Instruction Cache Functionality Instruction CacheData Cache Instruction Cache OperationInstruction Cache Software Support MSR BitData Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Format RoundingOperations ArithmeticHardware Acceleration using FSL Fast Simplex Link FSLExceptions ComparisonTrace Overview Debug and TraceDebug Overview MicroBlaze Architecture MicroBlaze I/O Overview IlmbIxcl DxclMicroBlaze Signal Interface Description Dmrnw DopbImrnw Iopb DAS DlmbIAS Ilmb MfslOn-Chip Peripheral Bus OPB Interface Description IxclmDxcls DxclmLMB Signal Interface ByteEnable03Local Memory Bus LMB Interface Description Addr031DataWrite031 ReadStrobeWriteStrobe DataRead031Generic Read Operation LMB TransactionsGeneric Write Operation Back-to-Back Write Operation Single Cycle Back-to-Back Read OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface Xilinx CacheLink XCL Interface Description FSL TransactionsFSL BUS Write Operation FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Debug Interface Description Trace Interface DescriptionDebug Interface Description MDMMicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind DescriptionValues Assigned Type Cusepcmpinstr CusemsrinstrPcmpne Cunalignedexception CnumberofrdaddrbrkCdcacheusefsl FfffCicacheusefsl Scope Data Types2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Formats Type aType B Opcode Destination Reg Source Reg a Immediate ValueRegisters Altered AddDescription Addi Registers Altered Latency RD, rA, rBAndi Logial and with Immediate Andi RD, rA, IMMAndn RD, rA, rB AndnLogical and not Andni Logical and not with Immediate Andni RD, rA, IMMBeqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Blt Branch if Less Than BltBltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Instructions Unconditional Branch BraBrd BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB MsrbipBrki Break Immediate Brki RD, IMMBsll Instructions Barrel Shift BsrlBsra Bsi Barrel Shift Immediate BsrliBsrai BslliCmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Fmul Floating Point Arithmetic Multiplication FmulFdiv Floating Point Arithmetic DivisionFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Get Get from fsl interfaceNget CgetIdivu IdivInteger Divide Idiv Imm Immediate ImmIMMLbu RD, rA, rB LbuLoad Byte Unsigned Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMMLhu Lhu RD, rA, rBLhui Load Halfword Unsigned Immediate Lhui RD, rA, IMMLoad Word Lwi Load Word Immediate Lwi RD, rA, IMMMfs Mfs RD, rSMsrclr Read MSR and clear bits in MSR Msrclr RD, ImmMsrset Msrset RD, ImmMts Move To Special Purpose Register Mts RS, rAInstructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMMLogical or Ori Logical or with Immediate Ori RD, rA, IMMPcmpbf Pattern Compare Byte Find PcmpbfPcmpeq Pattern Compare Equal PcmpeqPcmpne Pattern Compare Not Equal PcmpnePut Put to fsl interfaceNput CputRsub Arithmetic Reverse Subtract RsubRsubc RsubkRsubi Arithmetic Reverse Subtract Immediate RsubiRsubic RsubikRtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Rtsd Return from Subroutine Rtsd RA, IMMNone Sbi Store Byte Immediate Sbi RD, rA, IMMSext16 Sext16 RD, rASext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMMSra Sra RD, rASrc Shift Right with Carry Src RD, rASrl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMMWdc Write to Data CacheWic Xor Logical Exclusive or Xor RD, rA, rBXori RA, rD, IMM XoriLogical Exclusive or with Immediate 148

Chapter 4: MicroBlaze Instruction Set Architecture

msrclr

Read MSR and clear bits in MSR

msrclr

rD, Imm

Description

Pseudocode

Registers Altered

•MSR

Latency

MicroBlaze Processor Reference Guide

UG081 (v6.0) June 1, 2006