Msrclr

Chapter 4: MicroBlaze Instruction Set Architecture

Read MSR and clear bits in MSR

msrclr

rD, Imm

1 0 0 1 0 1

0 0 0 0 1

0 0

Imm14

16 17 18

Description

Copies the contents of the special purpose register MSR into register rD.

Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the IMM value are left untouched.

Pseudocode

(rD) ← (MSR)

(MSR) ← (MSR) ∧ ( IMM))

Registers Altered

•rD

•MSR

Latency

1 cycle

Note

MSRCLR will affect some MSR bits immediately (e.g. Carry) while the remaining bits will take effect one cycle after the instruction has been executed.

The immediate values has to be less than 214. Only bits 18 to 31 of the MSR can be cleared.

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Xilinx EDK 8.2i manual Read MSR and clear bits in MSR Msrclr RD, Imm

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions MSR ESREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers General Purpose Registers Special Purpose RegistersProgram Counter PC Registers 8Program Counter PC Bits Name Description Reset Value Machine Status Register MSR9Machine Status Register MSR Bits Name Description PVR EIP DCEICE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR CFG CusebarrelDIV Cusediv Cdebugenabled OP0EXECUnexec Cunalignedexception Icll CicachelinelenIcbs Ccachebytesize Cresetmsr Pipeline ArchitectureArch Rstmsr Branches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Reset Hardware ExceptionsEquivalent Pseudocode Exception Causes Breaks Hardware Breaks Interrupt User Vector ExceptionSoftware Breaks Latency Instruction Cache OverviewGeneral Instruction Cache Functionality Instruction Cache Data Cache Instruction Cache OperationInstruction Cache Software Support MSR Bit Data Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Format RoundingOperations Arithmetic Hardware Acceleration using FSL Fast Simplex Link FSLExceptions Comparison Trace Overview Debug and TraceDebug Overview MicroBlaze Architecture MicroBlaze I/O Overview IlmbIxcl Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb Imrnw Iopb DAS DlmbIAS Ilmb Mfsl On-Chip Peripheral Bus OPB Interface Description IxclmDxcls Dxclm LMB Signal Interface ByteEnable03Local Memory Bus LMB Interface Description Addr031 DataWrite031 ReadStrobeWriteStrobe DataRead031 Generic Read Operation LMB TransactionsGeneric Write Operation Back-to-Back Write Operation Single Cycle Back-to-Back Read OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface Xilinx CacheLink XCL Interface Description FSL TransactionsFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Debug Interface Description Trace Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Cusepcmpinstr CusemsrinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Cdcacheusefsl FfffCicacheusefsl Scope Data Types 2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Formats Type aType B Opcode Destination Reg Source Reg a Immediate Value Registers Altered AddDescription Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Andn RD, rA, rB AndnLogical and not Andni Logical and not with Immediate Andni RD, rA, IMM Beqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Blt Branch if Less Than Blt Bltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Instructions Unconditional Branch BraBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Bsll Instructions Barrel Shift BsrlBsra Bsi Barrel Shift Immediate BsrliBsrai Bslli Cmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Fmul Floating Point Arithmetic Multiplication Fmul Fdiv Floating Point Arithmetic DivisionFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get Get from fsl interfaceNget Cget Idivu IdivInteger Divide Idiv Imm Immediate ImmIMM Lbu RD, rA, rB LbuLoad Byte Unsigned Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Put Put to fsl interfaceNput Cput Rsub Arithmetic Reverse Subtract RsubRsubc Rsubk Rsubi Arithmetic Reverse Subtract Immediate RsubiRsubic Rsubik Rtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Srl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Xori RA, rD, IMM XoriLogical Exclusive or with Immediate 148

Chapter 4: MicroBlaze Instruction Set Architecture

msrclr

Read MSR and clear bits in MSR

msrclr

rD, Imm

Description

Pseudocode

Registers Altered

•MSR

Latency

MicroBlaze Processor Reference Guide

UG081 (v6.0) June 1, 2006