Xilinx EDK 8.2i manual CacheLink Signal Interface

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Chapter 2: MicroBlaze Signal Interface Description

The MicroBlaze CacheLink interface can also connect to an Fast Simplex Link (FSL) interfaced memory controller via explicitly instantiated FSL master/slave pair, however this topology is considered deprecated and is not recommended for new designs.

The interface is only available on MicroBlaze when caches are enabled. It is legal to use a CacheLink cache on the instruction side or the data side without caching the other. Memory locations outside the cacheable range are accessed over OPB or LMB. Cached memory range is accessed over OPB whenever the caches are software disabled (i.e. MSR[DCE]=0 or MSR[ICE]=0).

The CacheLink cache controllers handle 4 or 8-word cache lines with critical word first. At the same time the separation from the OPB bus reduces contention for non-cached memory accesses.

CacheLink Signal Interface

The CacheLink signals on MicroBlaze are listed in Table 2-8

Table 2-8:MicroBlaze Cache Link signals

Signal Name	Description	VHDL Type	Direction
ICACHE_FSL_IN_Clk	Clock output to I-side	std_logic	output
	return read data FSL
ICACHE_FSL_IN_Read	Read signal to I-side	std_logic	output
	return read data FSL.
ICACHE_FSL_IN_Data	Read data from I-side	std_logic_vector	input
	return read data FSL	(0 to 31)
ICACHE_FSL_IN_Control	FSL control-bit from I-	std_logic	input
	side return read data FSL.
	Reserved for future use
ICACHE_FSL_IN_Exists	More read data exists in I-	std_logic	input
	side return FSL
ICACHE_FSL_OUT_Clk	Clock output to I-side	std_logic	output
	read access FSL
ICACHE_FSL_OUT_Write	Write new cache miss	std_logic	output
	access request to I-side
	read access FSL
ICACHE_FSL_OUT_Data	Cache miss access	std_logic_vector	output
	(=address) to I-side read	(0 to 31)
	access FSL
ICACHE_FSL_OUT_Control	FSL control-bit to I-side	std_logic	output
	read access FSL. Reserved
	for future use
ICACHE_FSL_OUT_Full	FSL access buffer for I-	std_logic	input
	side read accesses is full
DCACHE_FSL_IN_Clk	Clock output to D-side	std_logic	output
	return read data FSL

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