Imrnw Iopb, DAS Dlmb, IAS Ilmb, Mfsl, Sfsl, Ixcls | Xilinx EDK 8.2i

MicroBlaze I/O Overview

Table 2-1:Summary of MicroBlaze Core I/O (Continued)

R

	Signal	Interface		I/O	Description

	IM_BE[0:3]	IOPB		O	Instruction interface OPB byte enables

	IM_busLock	IOPB		O	Instruction interface OPB bus lock

	IM_DBus[0:31]	IOPB		O	Instruction interface OPB write data bus
					(always 0x00000000)

	IM_request	IOPB		O	Instruction interface OPB bus request

	IM_RNW	IOPB		O	Instruction interface OPB read, not write
					(tied to IM_select)

	IM_select	IOPB		O	Instruction interface OPB select

	IM_seqAddr	IOPB		O	Instruction interface OPB sequential
					address

	IOPB_DBus[0:31]	IOPB		I	Instruction interface OPB read data bus

	IOPB_errAck	IOPB		I	Instruction interface OPB error
					acknowledge

	IOPB_MGrant	IOPB		I	Instruction interface OPB bus grant

	IOPB_retry	IOPB		I	Instruction interface OPB bus cycle retry

	IOPB_timeout	IOPB		I	Instruction interface OPB timeout error

	IOPB_xferAck	IOPB		I	Instruction interface OPB transfer
					acknowledge

	Data_Addr[0:31]	DLMB		O	Data interface LMB address bus

	Byte_Enable[0:3]	DLMB		O	Data interface LMB byte enables

	Data_Write[0:31]	DLMB		O	Data interface LMB write data bus

	D_AS	DLMB		O	Data interface LMB address strobe

	Read_Strobe	DLMB		O	Data interface LMB read strobe

	Write_Strobe	DLMB		O	Data interface LMB write strobe

	Data_Read[0:31]	DLMB		I	Data interface LMB read data bus

	DReady	DLMB		I	Data interface LMB data ready

	Instr_Addr[0:31]	ILMB		O	Instruction interface LMB address bus

	I_AS	ILMB		O	Instruction interface LMB address
					strobe

	IFetch	ILMB		O	Instruction interface LMB instruction
					fetch

	Instr[0:31]	ILMB		I	Instruction interface LMB read data bus

	IReady	ILMB		I	Instruction interface LMB data ready

	FSL0_M .. FSL7_M	MFSL		O	Master interface to output FSL channels

	FSL0_S .. FSL7_S	SFSL		I	Slave interface to input FSL channels

	ICache_FSL_in...	IXCL_S		IO	Instruction side CacheLink FSL slave
					interface


MicroBlaze Processor Reference Guide		www.xilinx.com			47
UG081 (v6.0) June 1, 2006		1-800-255-7778

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Xilinx EDK 8.2i manual Imrnw Iopb, DAS Dlmb, IAS Ilmb, Mfsl, Sfsl, Ixcls

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness FSR MSRESR EAR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PC PVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name Description FSL EIPDCE ICE Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusediv CFGCusebarrel DIV Cunalignedexception CdebugenabledOP0EXEC Unexec Ccachebytesize IcllCicachelinelen Icbs Rstmsr CresetmsrPipeline Architecture Arch Branches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Exception Causes ResetHardware Exceptions Equivalent Pseudocode Hardware Breaks Breaks Latency InterruptUser Vector Exception Software Breaks Instruction Cache Instruction CacheOverview General Instruction Cache Functionality MSR Bit Data CacheInstruction Cache Operation Instruction Cache Software Support Data Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Arithmetic FormatRounding Operations Comparison Hardware Acceleration using FSLFast Simplex Link FSL Exceptions Trace Overview Debug and TraceDebug Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb Ixcl Dmrnw Dopb MicroBlaze Signal Interface Description Mfsl Imrnw IopbDAS Dlmb IAS Ilmb Dxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxcls Addr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface Description DataRead031 DataWrite031ReadStrobe WriteStrobe Generic Read Operation LMB TransactionsGeneric Write Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write Operation CacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss MDM Debug Interface DescriptionTrace Interface Description Debug Interface Description MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne Cunalignedexception Cdcacheusefsl FfffCicacheusefsl Data Types Scope 2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type B Registers Altered AddDescription Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Andn RD, rA, rB AndnLogical and not Logical and not with Immediate Andni RD, rA, IMM Andni Beqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Branch if Less Than Blt Blt Bltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Brad Instructions Unconditional BranchBra Brd MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Bsll Instructions Barrel Shift BsrlBsra Bslli BsiBarrel Shift Immediate Bsrli Bsrai Cmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Floating Point Arithmetic Multiplication Fmul Fmul Esrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB Divide Fcmp Esrec FSRIO,DO Cget GetGet from fsl interface Nget Idivu IdivInteger Divide Idiv Immediate ImmIMM Imm Lbu RD, rA, rB LbuLoad Byte Unsigned Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Cput PutPut to fsl interface Nput Rsubk RsubArithmetic Reverse Subtract Rsub Rsubc Rsubik RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubic Rtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Srl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Xori RA, rD, IMM XoriLogical Exclusive or with Immediate 148