Branch if Equal Beq, Beqd | Xilinx EDK 8.2i guide

Instructions

beq	Branch if Equal
	beq	rA, rB	Branch if Equal
	beqd	rA, rB	Branch if Equal with Delay

R

1 0 0 1 1 1

D 0 0 0 0

rA

rB

0 0 0 0 0 0 0 0 0 0 0

0

6

11

16

21

31

Description

Branch if rA is equal to 0, to the instruction located in the offset value of rB. The target of the branch will be the instruction at address PC + rB.

The mnemonic beqd will set the D bit. The D bit determines whether there is a branch delay slot or not. If the D bit is set, it means that there is a delay slot and the instruction following the branch (i.e. in the branch delay slot) is allowed to complete execution before executing the target instruction. If the D bit is not set, it means that there is no delay slot, so the instruction to be executed after the branch is the target instruction.

Pseudocode

If rA = 0 then PC ← PC + rB

else

PC ← PC + 4 if D = 1 then

allow following instruction to complete execution

Registers Altered

•PC

Latency

1 cycle (if branch is not taken)

2 cycles (if branch is taken and the D bit is set)

3 cycles (if branch is taken and the D bit is not set)

Note

A delay slot must not be used by the following: IMM, branch, or break instructions. This also applies to instructions causing recoverable exceptions (e.g. unalignement), when hardware exceptions are enabled. Interrupts and external hardware breaks are deferred until after the delay slot branch has been completed.

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UG081 (v6.0) June 1, 2006	1-800-255-7778

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Xilinx EDK 8.2i manual Branch if Equal Beq, Beqd

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness FSR MSRESR EAR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Registers General Purpose RegistersSpecial Purpose Registers Program Counter PC PVR 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR 9Machine Status Register MSR Bits Name Description FSL EIPDCE ICE Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusediv CFGCusebarrel DIV Cunalignedexception CdebugenabledOP0EXEC Unexec Ccachebytesize IcllCicachelinelen Icbs Rstmsr CresetmsrPipeline Architecture Arch Memory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Exception Causes ResetHardware Exceptions Equivalent Pseudocode Hardware Breaks Breaks Latency InterruptUser Vector Exception Software Breaks Instruction Cache Instruction CacheOverview General Instruction Cache Functionality MSR Bit Data CacheInstruction Cache Operation Instruction Cache Software Support Data Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Arithmetic FormatRounding Operations Comparison Hardware Acceleration using FSLFast Simplex Link FSL Exceptions Debug Overview Debug and TraceTrace Overview MicroBlaze Architecture Dxcl MicroBlaze I/O OverviewIlmb Ixcl Dmrnw Dopb MicroBlaze Signal Interface Description Mfsl Imrnw IopbDAS Dlmb IAS Ilmb Dxclm On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxcls Addr031 LMB Signal InterfaceByteEnable03 Local Memory Bus LMB Interface Description DataRead031 DataWrite031ReadStrobe WriteStrobe Generic Write Operation LMB TransactionsGeneric Read Operation BE0 BE1 BE2 Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation Back-to-Back Mixed Read/Write Operation RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL BUS Read Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Write Operation CacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write MDM Debug Interface DescriptionTrace Interface Description Debug Interface Description MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cnumberofrdaddrbrk CusepcmpinstrCusemsrinstr Pcmpne Cunalignedexception Cicacheusefsl FfffCdcacheusefsl Data Types Scope MicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Opcode Destination Reg Source Reg a Immediate Value FormatsType a Type B Description AddRegisters Altered Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Logical and not AndnAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM Andni Branch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Branch if Less Than Blt Blt Blti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Brad Instructions Unconditional BranchBra Brd MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Bsra Instructions Barrel Shift BsrlBsll Bslli BsiBarrel Shift Immediate Bsrli Bsrai Integer Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul Fmul Esrec FSRIO,UF,OF,DO,DZ FdivFloating Point Arithmetic Division Fdiv RD, rA, rB Divide Fcmp Esrec FSRIO,DO Cget GetGet from fsl interface Nget Integer Divide Idiv IdivIdivu Immediate ImmIMM Imm Load Byte Unsigned LbuLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Cput PutPut to fsl interface Nput Rsubk RsubArithmetic Reverse Subtract Rsub Rsubc Rsubik RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubic Return from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Shift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Logical Exclusive or with Immediate XoriXori RA, rD, IMM 148