R

Chapter 2: MicroBlaze Signal Interface Description

Back-to-Back Write Operation

Clk

 

 

 

Addr

A0

A1

A2

Byte_Enable

BE0

BE1

BE2

Data_Write

 

 

 

AS

Read_Strobe

Write_Strobe

Data_Read

Ready

Figure 2-4:LMB Back-to-Back Write Operation

Single Cycle Back-to-Back Read Operation

Clk

 

 

 

 

 

 

 

 

 

 

Addr

 

 

A0

 

A1

A2

 

 

Byte_Enable

 

 

BE0

 

BE1

BE2

 

 

Data_Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AS

 

 

 

 

 

 

 

 

 

 

Read_Strobe

 

 

 

 

 

 

 

 

 

 

Write_Strobe

 

 

 

 

 

 

 

 

 

 

Data_Read

 

 

 

 

D0

D1

D2

Ready

 

 

 

 

 

 

 

 

 

 

Figure 2-5:LMB Single Cycle Back-to-Back Read Operation

Back-to-Back Mixed Read/Write Operation

 

 

 

 

Clk

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Addr

 

 

A0

A1

 

 

 

 

Byte_Enable

 

 

BE0

BE1

 

 

 

 

Data_Write

 

 

D0

 

 

 

 

 

 

 

AS

 

 

 

 

 

 

 

 

 

 

Read_Strobe

 

 

 

 

 

 

 

 

 

 

Write_Strobe

 

 

 

 

 

 

 

 

 

 

Data_Read

 

 

 

 

 

 

D1

 

 

Ready

 

 

 

 

 

 

 

 

 

 

Figure 2-6:Back-to-Back Mixed Read/Write Operation

52

www.xilinx.com

MicroBlaze Processor Reference Guide

 

1-800-255-7778

UG081 (v6.0) June 1, 2006

Page 52
Image 52
Xilinx EDK 8.2i manual Back-to-Back Write Operation, Single Cycle Back-to-Back Read Operation, BE0 BE1 BE2