MicroBlaze Core Configurability
Table
R
Signal Name |
| Description |
| VHDL Type | Direction |
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Trace_OF_PipeRun | Pipeline advance for |
| std_logic | output | |
| Decode stage |
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| |
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Trace_EX_PipeRun | Pipeline advance for |
| std_logic | output | |
| Execution stage |
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| |
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Trace_MEM_PipeRun | Pipeline advance for |
| std_logic | output | |
| Memory stage |
|
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| |
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1. Valid only when Trace_Valid_Instr = 1 |
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Table |
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Trace_Exception_Kind [0:3] |
| Description |
| ||
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0001 |
| Unaligned execption |
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0010 |
| Illegal Opcode exception |
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0011 |
| Instruction Bus exception |
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0100 |
| Data Bus exception |
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0101 |
| Div by Zero exception |
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0110 |
| FPU exception |
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1001 |
| Debug exception |
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1010 |
| Interrupt |
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1011 |
| External non maskable break |
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1100 |
| External maskable break |
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MicroBlaze Core Configurability
The MicroBlaze core has been developed to support a high degree of user configurability. This allows tailoring of the processor to meet specific cost/performance requirements.
Configuration is done via parameters that typically: enable, size, or select certain processor features. E.g. the instruction cache is enabled by setting the C_USE_ICACHE parameter. The size of the instruction cache, and the cacheable memory range, are all configurable using: C_CACHE_BYTE_SIZE, C_ICACHE_BASEADDR, and C_ICACHE_HIGHADDR respectively.
MicroBlaze Processor Reference Guide | www.xilinx.com | 61 |
UG081 (v6.0) June 1, 2006 |
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