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Xilinx EDK 8.2i manual Overview, General Instruction Cache Functionality, Bram

Models: EDK 8.2i

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Instruction Cache

R

PC ← 0x00000008

Instruction Cache

Overview

MicroBlaze may be used with an optional instruction cache for improved performance when executing code that resides outside the LMB address range.

The instruction cache has the following features:

•Direct mapped (1-way associative)

•User selectable cacheable memory address range

•Conﬁgurable cache and tag size

•Caching over CacheLink (XCL) interface

•Option to use 4 or 8 word cache-line

•Cache on and off controlled using a bit in the MSR

•Optional WIC instruction to invalidate instruction cache lines

General Instruction Cache Functionality

When the instruction cache is used, the memory address space in split into two segments: a cacheable segment and a non-cacheable segment. The cacheable segment is determined by two parameters: C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR. All addresses within this range correspond to the cacheable address segment. All other addresses are non-cacheable.

Instruction Address Bits

0

Tag Address

Cache Address

30 31

- -

Line Addr	Tag	Tag	Cache_Hit
		=
	BRAM	Valid (word and line)

Word Addr	Instruction		Cache_instruction_data
	BRAM

Figure 1-9:Instruction Cache Organization

The cacheable instruction address consists of two parts: the cache address, and the tag address. The MicroBlaze instruction cache can be conﬁgured from 2kB to 64 kB. This corresponds to a cache address of between 11 and 16 bits. The tag address together with the cache address should match the full address of cacheable memory.

MicroBlaze Processor Reference Guide	www.xilinx.com	37
UG081 (v6.0) June 1, 2006	1-800-255-7778

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Xilinx EDK 8.2i manual Overview, General Instruction Cache Functionality, Bram

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference GuideMicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual ContentsTypographical ConventionsConventions Meaning or Use Example Online DocumentUG081 v6.0 June 1 Overview FeaturesVersion Status Deprecated Active MicroBlaze ArchitectureInstructions Data Types and EndiannessESR MSREAR FSROp1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Special Purpose Registers General Purpose RegistersProgram Counter PC RegistersMachine Status Register MSR 8Program Counter PC Bits Name Description Reset Value9Machine Status Register MSR Bits Name Description PVRDCE EIPICE FSLException Address Register EAR Buslock EnableESS Exception Status Register ESRSource/Destination Register Branch Target Register BTRProcessor Version Register PVR Floating Point Status Register FSRCusebarrel CFGDIV CusedivOP0EXEC CdebugenabledUnexec CunalignedexceptionCicachelinelen IcllIcbs CcachebytesizePipeline Architecture CresetmsrArch RstmsrMemory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and BreakHardware Exceptions ResetEquivalent Pseudocode Exception CausesHardware Breaks BreaksUser Vector Exception InterruptSoftware Breaks LatencyOverview Instruction CacheGeneral Instruction Cache Functionality Instruction CacheInstruction Cache Operation Data CacheInstruction Cache Software Support MSR BitData Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Rounding FormatOperations ArithmeticFast Simplex Link FSL Hardware Acceleration using FSLExceptions ComparisonDebug Overview Debug and TraceTrace Overview MicroBlaze Architecture Ilmb MicroBlaze I/O OverviewIxcl DxclDmrnw Dopb MicroBlaze Signal Interface DescriptionDAS Dlmb Imrnw IopbIAS Ilmb MfslIxclm On-Chip Peripheral Bus OPB Interface DescriptionDxcls DxclmByteEnable03 LMB Signal InterfaceLocal Memory Bus LMB Interface Description Addr031ReadStrobe DataWrite031WriteStrobe DataRead031Generic Write Operation LMB TransactionsGeneric Read Operation Single Cycle Back-to-Back Read Operation Back-to-Back Write OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL Transactions Xilinx CacheLink XCL Interface DescriptionFSL BUS Write Operation FSL BUS Read OperationCacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write Trace Interface Description Debug Interface DescriptionDebug Interface Description MDMMicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core ConﬁgurabilityValues Assigned Type Cusemsrinstr CusepcmpinstrPcmpne Cunalignedexception CnumberofrdaddrbrkCicacheusefsl FfffCdcacheusefsl Data Types ScopeMicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack ConventionHigh Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Type a FormatsType B Opcode Destination Reg Source Reg a Immediate ValueDescription AddRegisters Altered Addi RD, rA, rB Registers Altered LatencyLogial and with Immediate Andi RD, rA, IMM AndiLogical and not AndnAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM AndniBranch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Branch if Less Than Blt BltBlti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Bra Instructions Unconditional BranchBrd BradMicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rBBreak Immediate Brki RD, IMM BrkiBsra Instructions Barrel Shift BsrlBsll Barrel Shift Immediate Bsrli BsiBsrai BslliInteger Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul FmulFloating Point Arithmetic Division FdivFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZFcmp Esrec FSRIO,DO Get from fsl interface GetNget CgetInteger Divide Idiv IdivIdivu Immediate ImmIMM ImmLoad Byte Unsigned LbuLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM LbuiLhu RD, rA, rB LhuLoad Halfword Unsigned Immediate Lhui RD, rA, IMM LhuiLoad Word Load Word Immediate Lwi RD, rA, IMM LwiMfs RD, rS MfsRead MSR and clear bits in MSR Msrclr RD, Imm MsrclrMsrset RD, Imm MsrsetMove To Special Purpose Register Mts RS, rA MtsInstructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM MuliLogical or Logical or with Immediate Ori RD, rA, IMM OriPattern Compare Byte Find Pcmpbf PcmpbfPattern Compare Equal Pcmpeq PcmpeqPattern Compare Not Equal Pcmpne PcmpnePut to fsl interface PutNput CputArithmetic Reverse Subtract Rsub RsubRsubc RsubkArithmetic Reverse Subtract Immediate Rsubi RsubiRsubic RsubikReturn from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Return from Subroutine Rtsd RA, IMM RtsdNone Store Byte Immediate Sbi RD, rA, IMM SbiSext16 RD, rA Sext16Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM ShiSra RD, rA SraShift Right with Carry Src RD, rA SrcShift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register AlteredWrite to Data Cache WdcWic Logical Exclusive or Xor RD, rA, rB XorLogical Exclusive or with Immediate XoriXori RA, rD, IMM 148